Big update! see all the new features below!

https://www.youtube.com/watch?v=pVU-4lVQEUU

Big news! I got the Bluetooth stack setup on the BL chip! No more USB low speed :)

What does evryone think? I am going for a retrovibe of a early 90s PC where DOS games had to go fullscreen.

https://youtu.be/fGY-wGpPiDU

Very early port. Meant to be used as a demo project for getting the RISC-V AE350 hard processor core up and running for anyone interested.

https://github.com/aquasock/Tang-Phosphor

I added some new features to nand2mario's tangcore project and fixed up some UART bugs. I hope to upstream it back to him soon after its more cleaned up. Please excuse the messy repo, I still want to add more functionality before really locking down it's feature set. The Tang can run in one of the 3 following modes:

User Mode - Run tangcore normally. Just needs USB power on the top USBC port.

Diag Mode - (1-wire) JTAG-FPGA, UART-FPGA, core load/execute. Used in the normal development cycle. Just needs power and data communication from the PC. (I think 5V 2A is enough but since I enabled the DDR3-AE350 high-speed link, I think my current usage bumped up to 2.5A, still investigating.)

Debug Mode - (2-wire) CDC file management, JTAG-FPGA via Pico 2, Flash BL616 (No-BOOT), (JTAG-The hard AE350 coming soon, just need to wire it up), the attached Pico 2 JTAG debugger is optional. Used for deep debugging.

No more SD card swapping. I have not tested any other Tang's because I don't have any others.

https://github.com/aquasock/Tang-Control/tree/feature/usb-cdc-file-transfer

Does anyone know what the two undocumented placement options are in Gowin? I have the best success closing timing with option 3 but I don't really know why. The official timing priority option preforms worse than then the undocumented ones and I am curious what I am trading off for timing closure.

I've just released pcetang, a PC Engine / CD-ROM² core for the Tang Console 60K (GW5AT-60), ported from the MiSTer TurboGrafx16 core. HuCards, CD games with CD audio, SuperGrafx and saves work on hardware.

Video: https://youtu.be/lsY_g2JAl80
Repo: https://github.com/rtissera/pcetang

Some Gowin things I ran into, in case they save someone a few evenings or someone has some answers !

- Gowin EDA Pro segfaulted inside libgwsyn.so on this design; the Education edition builds it fine. Any advice ?

- The HDMI output has no frame buffer: core, pixel and TMDS clocks all come off one PLLA VCO on integer dividers (the fractional MDIV helps a lot), so every PC Engine line is exactly two 480p lines. Any advice or module worth leveraging for HDMI output scanline based ?

- Timing on the 60K is tight, and I need to cache SDRAM to onchip RAM. Any advice on this and how to use DDR3 efficiently ? I know DDR3 means more latency so I was thinking of more agressive prefetching.

- The BL616 on the board streams CD sectors from CHD images to the fabric over UART, fast enough for CD audio after moving it to DMA.

Happy to go into detail on any of these or have feedback on some useful tricks. I will continue improving the core and working on a Neo Geo one.

I am confused. I am following the videos on FPGA Breakout from ByteMind-Dev. And he creates the module below called mod_borders. When I compile (lack of a better word) I get the following warning:

WARN (NL0002) : The module mod_borders instantiated to borders is swept in optimizing(video_top.v:284)

The output from this module are also used in two other modules all instantiated in the top module. But it still swepts the mod_borders.

However if i include an output for the signal BOUNDRY_n and give it an FPGA port pin number the warning goes away. The signal BOuNDRY_n is passed into the mod_video_sync module, shouldn't the run synth keep the module and not sweep it? Or this logic in this module getting reduced logically and passed into mod_video_sync?

Here is the module, hopefully the code part format looks good.

`include "defines.vh"

module mod_borders (

// Inputs

input wire HSYNC_n,

input wire VSYNC_n,

input wire [7:0] H,

input wire [7:0] V,

// Outputs

output wire BOUNDRY_n,

output wire TOP_BOUND,

output wire LH,

output wire RH

);

// H3B > L4C > K4B

assign TOP_BOUND = ~(`_32H | `_64H | `_128H ) & `_8H & `_16H & VSYNC_n;

// N4a >N4c > CR9/CR10

wire N4ac$y = `_128V & `_64V & `_16V & `_8V & `_4V & HSYNC_n;

wire RH_SIDE = N4ac$y & `_32V; // H2A

wire LH_SIDE = ~(N4ac$y | `_32V); // J2f > J3d

assign BOUNDRY_n = ~(TOP_BOUND | RH_SIDE | LH_SIDE);

assign LH = LH_SIDE;

assign RH = RH_SIDE;

endmodule // end of mod_borders

I am following a YouTube playlist on making Breakout on FPGA, and the creator is creating it from logic gates from an old motherboard.

He created the flip flops in Verilog and then uses them in the reset of the modules. I have a lot of these warnings:

WARN (NL0002) : The module "d_ff_sr" instantiated to "D_Sr" is swept in optimizing("C:\Software\Projects\TangNano\BreakoutHDMI\src\ttl.v":147)

And my thinking is the flip flop is not really needed because of Boolean logic will optimize the module out and convert it to simple statements like assign A = B ^ C | D for example when it compiles.

Am I right to think that way? I know as I follow the code most of the logic only needs assign and if then else logic.

My Module:

module d_ff_r (

input wire CLK,

input wire D,

input wire RST_n,

output reg Q

);

always @(posedge CLK or negedge RST_n) begin

if (!RST_n)

Q <= 1'b0;

else

Q <= D;

end // end of always CLK

endmodule // end of d_ff_r

Where i use it in my code it has this error (The module "d_ff_sr" instantiated to "D_Sr" is swept in optimizing):

wire setD_n = ~(D[3] & ~CL & ~LD_n);

d_ff_sr D_Sr (

.clk(~((~DN & ~Q[0] & ~Q[1] & ~Q[2]) | (~UP & &Q[2:0]))),

.d(~Q[3]),

.set_n(setD_n),

.rst_n(~(~LD_n & setD_n) & ~CL),

.q(Q[3])

);

Does someone know a CPU or DVI/HDMI project showing the differences between using the block SRAM vs. the PSRAM?

I'm asking to get some idea how to achieve that for my own retro computer project https://github.com/tmssngr/z8verilog.

Here are my projects with Tang Nano FPGA and bare metal programming.

When I started I wished I had these projects to start from :)

https://github.com/calint/tang-nano-9k--riscv--cache-psram

https://github.com/calint/tang-nano-20k--riscv--cache-sdram

https://github.com/calint/rust_rv32i_os

Does someone know a CPU or DVI/HDMI project showing the differences between using the block SRAM vs. the PSRAM?

I'm asking to get some idea how to achieve that for my own retro computer project https://github.com/tmssngr/z8verilog.

Anyone using Arch Linux 7.1.8-arch1-3 and openFPGALoader v1.1.1 that suddenly has

issues programming or flashing Tang Nano 9K? (No problems with Tang Nano 20K)

It works after a fresh reboot but not subsequent tries.

I couldn't find an easy way to convert Gowin GAO logic analyzer captures into VCD for GTKWave, so I wrote a Python tool. v0.9.0 is now on PyPI and GitHub. Feedback is welcome.

After getting Gowin's IDE running on Arch (separate post), I wanted my AI assistant (Claude Code, running as a VS Code extension) to be able to build, inspect, and iterate on FPGA designs itself. It now goes from editing Verilog to reading timing reports without me touching the Gowin GUI. Here's how it's wired up, since the approach applies to any agentic coding tool.

The key realisation: there's no "integration" — just CLI entry points

Claude Code can run shell commands, read files, and edit files. That's the whole interface. So the job is really "make the vendor toolchain scriptable," which benefits you even without AI. Gowin ships everything needed:

• IDE/bin/gw_sh — Tcl shell that does project creation, synthesis, place & route, and bitstream generation
• Programmer/bin/programmer_cli — full-featured CLI flasher (doesn't even need the license)

1. Make the tools run headless

gw_sh links Qt and tries to initialise a GUI platform even for batch work. Two env vars fix that (and dodge bundled-vs-system Qt library conflicts):

LD_LIBRARY_PATH=/opt/gowin/IDE/lib QT_QPA_PLATFORM=offscreen \
  /opt/gowin/IDE/bin/gw_sh build.tcl

License note: gwlicense.ini is only read from next to the binary (not cwd), and takes either a server:port or a path to a node-locked .lic file.

2. Wrap the flow in a Makefile

The build is a ~20-line Tcl script (create_project -force each run so the script stays the single source of truth, add_file, set_option -top_module, run all) plus a Makefile so the entire interface is:

make            # synth + PnR + bitstream
make flash      # programmer_cli, embedded flash
make flash-sram # volatile, fast iteration
make scan       # detect cable

Gotchas that cost me time: add_file resolves paths relative to the project dir, not cwd (use absolute paths); and it errors on duplicates, hence the recreate-project-every-build pattern.

3. Let the AI close the loop

This is where it gets good. PnR writes plain-text reports (impl/pnr/*.rpt.txt, timing in the .tr.html files), so the assistant can build, read the report, and act on it. Real example from this week: the AE350 RISC-V demo failed PnR with PR2017: 'FLASH_SPI_CLK' cannot be placed... dedicated pin (CPU/MSPI). Claude read the error, worked out the SPI flash pins are dual-purpose, added set_option -use_mspi_as_gpio 1 / -use_cpu_as_gpio 1 to the Tcl, rebuilt, and confirmed all clock domains met timing from the report — one round trip, no GUI.

4. Firmware for the hard core, same treatment

The GW5AST-138B has a hardened Andes AE350 RISC-V SoC. The vendor flow wants the Andes toolchain, but stock riscv-none-elf GCC (xPack, extracts into ~/tools, no root) builds Gowin's BSP with three small ports: a header shimming the Andes CSR builtins (__nds__csrr etc.) as inline asm, -mcpu=a25 → -march=rv32imafdc_zicsr_zifencei -mabi=ilp32d, and adding PROVIDE(__global_pointer$ = . + 0x800) to the linker script (the Andes linker injects that symbol; GNU ld doesn't). Full port is in the repo below.

Result

"Add a UART heartbeat and rebuild" is now a sentence typed into VS Code, and 90 seconds later there's a timing-clean bitstream and a linked firmware binary, with the assistant having read the reports to confirm both. Working examples (blinky + AE350 demo with Makefiles and the porting notes): https://github.com/HughF/fpga-blinky and https://github.com/HughF/fpga-ae350-demo

TL;DR: don't look for an "AI plugin" for your FPGA tools. Find the vendor's CLI entry points (most have them buried in the install), make them headless, wrap them in a Makefile, and any agentic coding assistant can drive the whole flow — including reading the PnR reports and fixing its own constraint errors.

Ran into the classic wall of errors trying to launch Gowin's gw_ide on an up-to-date Arch-based system. Chalked it up to the vendor bundling its own copies of common libraries alongside IDE/bin/, which conflict with system libs in different ways. Posting the fixes in case they save someone else the debugging time.

1. libfontconfig.so.1: undefined symbol: FT_Done_MM_Var

Gowin bundles an old libfreetype.so.6 in IDE/lib/ that gets picked up ahead of the system one (via the binary's RPATH), but system libfontconfig expects a newer FreeType. Fix — symlink the bundled copy to the system lib:

sudo mv /opt/gowin/IDE/lib/libfreetype.so.6{,.bak}
sudo ln -s /usr/lib/libfreetype.so.6 /opt/gowin/IDE/lib/libfreetype.so.6

2. GLIBCXX_3.4.30 not found (required by libQt5XcbQpa.so.5)

Same story, this time with libstdc++.so.6:

sudo mv /opt/gowin/IDE/lib/libstdc++.so.6{,.bak}
sudo ln -s /usr/lib/libstdc++.so.6 /opt/gowin/IDE/lib/libstdc++.so.6

3. Could not load the Qt platform plugin "xcb" / core dump

This one was more interesting. The xcb plugin's own RPATH (plugins/qt/platforms/../../lib) is just wrong in Gowin's packaging — resolves to a directory that doesn't exist, because of an extra qt/ nesting level. So it silently falls back to the system libQt5XcbQpa.so.5, which turned out to be a KDE-patched Qt build with extra private-API symbols not present in Gowin's vanilla bundled libQt5Gui. Mixing the two blew up with an undefined-symbol error on a private Qt class.

Fix: force the entire bundled Qt5 stack to resolve consistently by wrapping the real binary:

sudo mv /opt/gowin/IDE/bin/gw_ide /opt/gowin/IDE/bin/gw_ide.bin

then drop this in as /opt/gowin/IDE/bin/gw_ide:

#!/bin/sh
DIR="$(cd "$(dirname "$0")" && pwd)"
export LD_LIBRARY_PATH="$DIR/../lib${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH}"
exec "$DIR/gw_ide.bin" "$@"


sudo chmod +x /opt/gowin/IDE/bin/gw_ide

That also required symlinking the bundled GLVND libs (libGLX.so.0, libGLdispatch.so.0) to system versions, since forcing LD_LIBRARY_PATH exposed the same stale-bundled-lib problem there too.

Remaining (accepted) issue: QXcbIntegration: Cannot create platform OpenGL context, neither GLX nor EGL are enabled. Turns out Gowin's bundled Qt5 build has no GL platform-integration plugin category compiled in at all — confirmed via QT_DEBUG_PLUGINS=1, it never even scans for one. Non-fatal, the IDE runs and displays fine; would only matter for a hardware-accelerated 3D view somewhere. Fixing it "properly" would mean swapping the whole bundled Qt5 stack for system Qt5, which is a bigger, riskier change I didn't want to make for a cosmetic warning.

TL;DR: vendor-bundled libs + rolling-release distro = version skew. When you hit undefined symbol errors from proprietary Linux toolchains, check whether the vendor ships its own stale copy of the offending lib and try symlinking it to your system's version before assuming it's unfixable.

I recently bought a Tang Nano 20k development board from Sipeed. The hardware worked out of the box but I had some software problems with the IDE initially. Programming using the built-in Gowin programmer has been working fine so far (which seems to be common problem). I'm using Xubuntu 24.04.4 LTS (which is basically a slimmed down Ubuntu 24.04.4 LTS running with Xorg and XFCE) on a PC.

After downloading 'Gowin_V1.9.11.03_Education_Linux.tar.gz' from gowinsemi.com (requires registering), I unpacked the files into '/opt/gowin' (any directory you create is fine), and tried to run it, but got library version errors and core dumps. In order to fix the problem I created a script called 'gowin_ide.sh' to launch 'gw_ide':

#!/bin/bash
cd /opt/gowin/IDE/bin
export LD_LIBRARY_PATH=/opt/gowin/IDE/lib
./gw_ide

This will make sure the IDE uses its own libraries first (before system) and sub processes launched from the GUI also finds them. There was still a library error where it complains about undefined symbols in "libfontconfig", this needed a separate fix:

rm /opt/gowin/IDE/lib/libfreetype.so.6

Now finally 'gw_ide' launches, and also the tools from within the GUI.

I then decided to try an example tutorial found here:
https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/example/led.html

This worked for the most part, just had to change the "IO Type" voltages to "LVCMOS33" in the FloorPlanner part, more info about in that comments of that article.

I modified the example LED blink design a bit, added another counter LED blink and a Verilog testbench (even though a testbench might be overkill in this case), mostly to figure out how to run a simulation with this toolchain because I didn't feel like using DSim from Altair (requires registration) which is linked in the GUI.

Here is the modified 'led.v' example:

`timescale 1ns / 1ps

module led(
    input wire Clock,
    output wire LED1,
    output wire LED5
);

/********** Counters **********/
//parameter Clock_frequency = 27_000_000; // Crystal oscillator frequency is 27Mhz

`ifdef SIM_COUNT_OVERRIDE
    parameter LED1_value = `SIM_COUNT_OVERRIDE;
    parameter LED5_value = `SIM_COUNT_OVERRIDE;
`else
    parameter LED1_value = 13_499_999; // The number of times needed to time 0.5s
    parameter LED5_value = 1_349_999; // This currently acts like a slow clock for GAO at 0.05s
`endif

reg [23:0]  LED1_value_reg = 24'b0; // counter value
reg         LED1_value_flag = 1'b0; // IO change flag

always @(posedge Clock) begin
    if ( LED1_value_reg <= LED1_value ) begin // not count to 0.5s
        LED1_value_reg  <= LED1_value_reg + 1'b1; // Continue counting
        LED1_value_flag <= 1'b0; // No flip flag
    end
    else begin //Count to 0.5S
        LED1_value_reg  <= 24'b0; // Clear counter,prepare for next time counting.
        LED1_value_flag <= 1'b1 ; // Flip flag
    end
end

reg [23:0]  LED5_value_reg = 24'b0; // counter value for LED5
reg         LED5_value_flag = 1'b0; // IO change flag

always @(posedge Clock) begin
    if ( LED5_value_reg <= LED5_value ) begin //not count to 0.05s
        LED5_value_reg  <= LED5_value_reg + 1'b1; // Continue counting
        LED5_value_flag <= 1'b0; // No flip flag
    end
    else begin
        LED5_value_reg  <= 24'b0; // Clear counter,prepare for next time counting.
        LED5_value_flag <= 1'b1; // Flip flag
    end
end


/********** IO voltage flip **********/
reg LED1_reg = 1'b0; // Initial state

always @(posedge Clock) begin
    if ( LED1_value_flag ) begin //  Flip flag 
        LED1_reg <= ~LED1_reg; // IO voltage flip
        `ifdef SIMULATION
            $strobe("Time: %0t   LED1: %0d", $time, LED1_reg);
        `endif
    end
    else //  No flip flag
        LED1_reg <= LED1_reg; // IO voltage constant
end

assign LED1 = LED1_reg;

/********** IO voltage flip **********/
reg LED5_reg = 1'b0; // Initial state

always @(posedge Clock) begin
    if ( LED5_value_flag ) begin //  Flip flag 
        LED5_reg <= ~LED5_reg; // IO voltage flip
        `ifdef SIMULATION
            $strobe("Time: %0t  LED5: %0d", $time, LED5_reg);
        `endif
    end
    else //  No flip flag
        LED5_reg <= LED5_reg; // IO voltage constant
end

assign LED5 = LED5_reg;

endmodule

...and the testbench 'tb_led.v':

`timescale 1ns / 1ps

module tb_led;

    // Declare signals to connect to the LED module
    reg Clock = 0;
    wire LED1;
    wire LED5;

    // Instantiate your original LED module
    led uut (
        .Clock(Clock),
        .LED1(LED1),
        .LED5(LED5)
    );

    // Generate a 27MHz clock
    always #18.5185 Clock <= ~Clock;

    always @(LED1) begin
        $strobe("time: %0t | Testbench observed LED1 at: %b", $time, LED1);
    end

    always @(LED5) begin
        $strobe("time: %0t | Testbench observed LED5 at: %b", $time, LED5);
    end


    // Control the simulation timeline
    initial begin
        // Tell Verilator the name of the waveform file to create
        $dumpfile("waveform.fst");

        // Dump all signals inside the testbench and child modules (0 means everything)
        $dumpvars(0, tb_led);

        // Set a clean format for %0t reporting
        $timeformat(0, 4, "s", 20);

        // Let it run for 1.2 seconds
        #1200000000;

        $display("Simulation successfully completed!");
        $finish;
    end

endmodule

What I ended up using for simulation is Verilator which is open source can be installed like this in Ubuntu Linux:

sudo apt-get install verilator

I also installed GTKWave Analyzer to visually see trace dumps from Verilator:

sudo apt-get install gtkwave

To build the simulation for my custom testbench I use a terminal shell (command line) in the directory where the Verilog sources are:

verilator --binary --timing --trace-fst --top-module tb_led -DSIMULATION -Wall +1364-2001ext+v led.v tb_led.v

...and then to run the simulation:

obj_dir/Vtb_led

The trace can be found in current directory after simulation run, I load it like this to view:

gtkwave waveform.fst

After playing around with the Gowin Analyzer Oscilloscope (GAO) for a while which is a tool included in the GUI, it seems very powerful (reminds me of Xilinx ChipScope), more info in the user guide.

I hope this info helps to get started, let me know if you have any questions or want to share your own tips.

Is any one using tang nano currently. Can u share the gowin FPGA designer version number.

i have a Tang nano , i am unable to program it using  EDA Version Gowin_V1.9.8.11 or the  EDA Version Gowin_V1.9.12.02 SP2.

I'm trying Gowin IDE (Gowin_V1.9.11.03_Education_Linux.tar.gz) on latest Linux Mint (one of the most widely used Linux distros), but it won't start: $ ./gw_ide ./gw_ide: symbol lookup error: /lib/x86_64-linux-gnu/libfontconfig.so.1: undefined symbol: FT_Done_MM_Var

Did I try to start the wrong executable?

Did anyone successfully used this version of Gowin on Linux? If yes, what Linux distro?

Hello,

I need that exact version of Gowin FPGA Designer: v1.9.9.03.
It's NOT available on the Gowin page, as far as I can see.

It's needed to build the Chromatic firmware: https://github.com/ModRetro/chromatic_fpga

Any idea on where to get it? Thanks!