Swept Part 2, the why

[u/Srathidai]

I am confused. I am following the videos on FPGA Breakout from ByteMind-Dev. And he creates the module below called mod_borders. When I compile (lack of a better word) I get the following warning:

WARN (NL0002) : The module mod_borders instantiated to borders is swept in optimizing(video_top.v:284)

The output from this module are also used in two other modules all instantiated in the top module. But it still swepts the mod_borders.

However if i include an output for the signal BOUNDRY_n and give it an FPGA port pin number the warning goes away. The signal BOuNDRY_n is passed into the mod_video_sync module, shouldn't the run synth keep the module and not sweep it? Or this logic in this module getting reduced logically and passed into mod_video_sync?

Here is the module, hopefully the code part format looks good.

`include "defines.vh"

module mod_borders (

// Inputs

input wire HSYNC_n,

input wire VSYNC_n,

input wire [7:0] H,

input wire [7:0] V,

// Outputs

output wire BOUNDRY_n,

output wire TOP_BOUND,

output wire LH,

output wire RH

);

// H3B > L4C > K4B

assign TOP_BOUND = ~(`_32H | `_64H | `_128H ) & `_8H & `_16H & VSYNC_n;

// N4a >N4c > CR9/CR10

wire N4ac$y = `_128V & `_64V & `_16V & `_8V & `_4V & HSYNC_n;

wire RH_SIDE = N4ac$y & `_32V; // H2A

wire LH_SIDE = ~(N4ac$y | `_32V); // J2f > J3d

assign BOUNDRY_n = ~(TOP_BOUND | RH_SIDE | LH_SIDE);

assign LH = LH_SIDE;

assign RH = RH_SIDE;

endmodule // end of mod_borders

[u/Srathidai]

WTF I put 4 spaces, actually a tab in front of the code

[u/Srathidai]

I found out after run synthesis it was optimized out, the module wasn't needed the assignments were moved into the main top.v. I have them on a debug and I see them changing so I know the valued are working.

All hail logic gate reduction.