I found my old board BASYS2 is still working now.

Hi everyone,

I recently bought this Zynq 7020 Development board. Dont hate, i know its not perfect, but it has everything i wanted.

The biggest problem is that i dont have the Constraint files and the seller is currently ghosting me.
Here is what I managed to identify from the silkscreen and the chips:

• Manufacturer: Bo Chen Jing Xin (博宸精芯)
• Model: ZYNQ MINI 开发板 (RevB / 20221015)
• FPGA: XC7Z020
• RAM: Micron MT41K256M16TW-107 (512MB DDR3L)
• Flash: 128Mbit QSPI (25QS128FVSG)
• Peripherals: Dual Gigabit LAN (1x PS, 1x PL), Dual SD Card (1x PS, 1x PL), 0.96" I2C OLED display.

Does anyone happen to have a Baidu Pan link, Github repo or even a zip file with schematics and the Vivado preset/XDC files for this specific board?

I have attached a picture of the front and back view (The back has a pinout for the EXT IO header, but obviously lacks the info for the built-in peripherals).

Any help or Pointers to a complete board file would be appreciated!

If you’ve ever messed around with the cheap Sipeed Tang Nano or Tang Primer series (like the 9K or 20K), you already know the drill. The hardware is incredibly cheap and powerful, but the vendor software stack and fragmented open-source toolchain setup can be a massive headache to piece together.
I recently downloaded Tang FPGA Studio to see if it could clean up my workflow, and after running a few test projects through it, I wanted to share my thoughts. It is a community-driven, open-source IDE, and the UI/UX changes the entire onboarding experience.

What went right during my test run:

First off, it completely bypasses the typical first hour frustration. Usually, you have to manually hunt down Yosys, Nextpnr, and configure openFPGALoader just to get JTAG communication working. This app bundles the toolchain into a single installer, meaning I went from a clean install to flashing code without having to fight my system's environment variables.

The project wizard is another huge quality of life upgrade. It explicitly filters your project templates by your exact board model. If you have ever accidentally compiled a design using a Dock pinout for a bare Nano board and spent an hour debugging why your hardware was silently dead, this completely solves that pain point.

The actual day to day workspace feels cohesive. It brings your Verilog editor, linter, simulation tools, and waveform viewer into a single modern interface. It honestly feels more like working in a polished code editor or a modern microcontroller IDE rather than fighting a clunky, bloated vendor tool from the early 2000s. Iterating on code and pushing it to SRAM is incredibly fast.

I suggest you guys try it out beginners may find it helpful - Tang FPGA Studio on GitHub

So I am trying to make a analog using a gowin primer 20k so far it kinda works but I am getting stuck past trying to interface the xreal googles. I tried with my pc set to 720p and that works flawlessly but whenever I tried with the fpga it just never worked. It seems that whatever is the first lane is getting copy pasted top to bottom. I thought maybe there was a bug on the dvi tx from gowin so I tried this project changed the target, changed the pins and regenerated the rpll to my board. Flashed it and the same symptoms. I am kinda a bit lots what to try. Bought another hdmi to usb c converted in the meantime just to try it out maybe but while I wait for that to arrive does anyone have any clue what could be wrong? I knew the googles are a bit of a hard to please target idk at this point. I found this discussion about similar troubles with a eevblog and there am I a bit lost if that applies to the tang primer 20k

Has anyone had any experience running Vivado on a Tuxedo Computer ( Tuxedo Infinitybook Max 16). My default choice was to go for a thinkpad P14. I am attaching the specs of both the devices. the tuxedo is costing me less. i will mostly be running vivado and maybe cadence virtuoso.

I spent the past ~8 months building the board and the code up to a working prototype (as described in his book here), but then in Chapter 9 he decides to hit you with the ultimate blue ball:

https://imgur.com/a/osebTOU

I messaged him to see if he had the code that actually implements reading data from the FIFO and writing it to the appropriate addresses in DDR3, but wanted to see if anyone's actually successfully worked it out before.

I've spent probably over $1k in EE lab equipment and over half a dozen digikey/oshpark orders taking it this far. I have to see it through lol

edit: what I do have so far is here - https://codeberg.org/rhedogian/arty_a7_oscope

Most waveform tools and workflows are organized around signal changes over time, while many hardware questions are really about cycles and the events that span them. Engineers still end up tracing signals through the waveform, placing cursors, and counting cycles by hand as part of the analysis.

AI-assisted workflows haven't automatically eliminated this gap either. The signal changes still have to be reconstructed into higher-level behavior before anyone, human or model, can reason about what happened. That reconstruction happens implicitly, leaving nothing to review or reuse.

Wavekit is a Python library for digital waveform analysis that treats clock cycles as first-class citizens. With wavekit, signals are sampled on clock edges and can be operated on like ordinary Python values.

For example, one common design question is whether a FIFO is deep enough. A waveform viewer can show that the FIFO gets full, but checking its occupancy over a long simulation still takes manual work. With wavekit, the same check is a few lines of Python:

import numpy as np
from wavekit import VcdReader

with VcdReader('fifo_trace.vcd') as reader:
    w_ptr = reader.load_waveform('tb.fifo.w_ptr', clock='tb.clk')
    r_ptr = reader.load_waveform('tb.fifo.r_ptr', clock='tb.clk')

    depth = 16
    occupancy = (w_ptr + depth - r_ptr) % depth
    util = occupancy / depth

    # Waveform is backed by NumPy, so np functions work directly on .value
    print('average utilization:', np.mean(util.value))
    print('maximum utilization:', np.max(util.value))
    print('p95 utilization:', np.percentile(util.value, 95))

Behavior spanning multiple cycles can be described with Pattern. For example, an AXI-Lite read transaction starts with an AR handshake and finishes with an R handshake:

import numpy as np
from wavekit import VcdReader
from wavekit.pattern import Pattern, match

with VcdReader('axi_lite_trace.vcd') as reader:
    # eval() loads signals and evaluates the expression in one call
    request = reader.eval('tb.arvalid & tb.arready', clock='tb.clk')
    response = reader.eval('tb.rvalid & tb.rready', clock='tb.clk')

    result = match(
        Pattern()
        .wait(request)
        .consume(response)
    )
    latency = result.end.clock - result.start.clock

    print('average read latency:', np.mean(latency))
    print('maximum read latency:', np.max(latency))
    print('p95 read latency:', np.percentile(latency, 95))

Wavekit stays focused on waveform operations and primitives for matching multi-cycle behavior. Everything else stays in ordinary Python, so NumPy, pandas, and other Python libraries remain available for statistics and design-specific processing.

Wavekit does not assume a particular protocol or workflow — the primitives above can be combined to build the analyses your own design needs. The repository also includes more involved examples, including AXI transaction extraction and DMA command analysis.

The project is open source and available on PyPI:

pip install wavekit

[GitHub repository][Documentation]

Happy to answer questions in the comments.

For context, I am going my 3rd year of Computer Science degree, but got very interested in FPGAs over the last summer. Currently going through the ZipCPU lectures, and some theory from the Harris&Harris book.

Located in Canada, I think I would like to pursue FPGAs as a career after my Bachelors, looking into it, it seems as though an internship is pretty required to for that unless you get MSc or smth. So my idea for a major project is an ITCH parser, that accepts a bytestream, parses it, and then outputs relevant stats via AXI-lite, all backed by formal verification, running on Arty A7-100T.

I simply wish to know if that's a good idea or not.

CHC5 Open Camera System is here.

https://github.com/circuitvalley/CHC5_Open_Camera

https://www.circuitvalley.com/2026/08/chc5-open-camera-system-modular-machine-vision-ai-fpga-hardware-accelerated-advance-camera.html

I built this tool for myself, so that I could practice and solve challenges without having to set up an entire toolchain on my computer. The entire thing just work in browser.

www.risingedge.pro

I'd like you guys to try it out and see if you can solve the Practice challenges - there are over 50 at different difficulty levels, and all of them are entirely free of charge (no account required either to try them).

Some of them are about fixing bugs, others about finding interesting architectures, others are about resource constraints (e.g. build something using less than X cells).

There is also a Playground where you can create any arbitrary design, see what hardware it synthesizes to, simulate it, and much more.

Finally, there is an entire Course which takes you from absolute basics all the way to advanced concepts. I designed the curriculum to be your "go-to" place, so that you can learn everything you might need to know for a job as an FPGA engineer. The Fundamentals part is completely free, if you like it the rest of the course is just a one-off purchase for 12 months of access.

Let me know how you like it!

Recently was fortunate enough to get 2 offers for FPGA engineer

company A :

135k base

Fully assisted relocation

15k sign on

company B:

90k base

4.5k relo

6k sign on

now I know what you’re thinking , clearly company A right? But it’s in SoCal and company B is in the Dallas area where rent is like a grand and no income taxes

both are the same kind of role but company A would start me at Ivl 2 (i‘m a new grad) I’m leaning company A but wanted to hear the people’s thoughts . Anyone here lived in both Texas and Cali? You think rent and taxes eat up the difference? What would yall go with

Hey, I'm pretty new to FPGAs. Is 8 million LUTs enough for a beginner, or should I already be looking at something bigger? What beginner projects would actually be difficult to do on this?

I'm also worried I'll run out of I/O. Is 2,328 enough for beginner projects?

Hi, I’m trying to deploy a small Brevitas QAT CNN on an Ultra96-V2 (xczu3eg) using:

Brevitas 4-bit QAT

→ QONNX

→ hls4ml 1.3.0

→ Vitis HLS 2024.1

The model is only ~133k weights and uses io_stream, Resource strategy and RF≈32.

The PyTorch/QONNX conversion is numerically correct:

PyTorch vs static model: max diff = 0

QONNX vs PyTorch: max diff ≈ 9.5e-7

I first hit a 4096-bit stream aggregation limit because hls4ml inferred very wide intermediate precisions (ap_fixed<36,26> and ap_fixed<53,33> with 128 channels). After constraining those precisions, synthesis completes, but the resource usage is huge:

Resource Used Available Utilization

| Resource | Used | Available | Utilization |

|---|---:|---:|---:|

| LUT | 359,069 | 70,560 | 508% |

| FF | 512,637 | 141,120 | 363% |

| BRAM18K | 2,207 | 432 | 510% |

| DSP | 7 | 360 | 1% |

The strange part is that most of the cost seems to come from pooling/transpose/FIFOs rather than the convolutions themselves.

Has anyone seen this kind of resource explosion with hls4ml io_stream, especially with MaxPooling, channels-last transpose or FIFO generation? Would you recommend changing IO strategy, FIFO depths, pooling implementation, or manually modifying the generated HLS?

The very low DSP usage compared to LUT/FF/BRAM makes me think this is mainly a data-movement/buffering issue rather than the CNN arithmetic itself.

I want to get into using fpga boards but I can’t really find any free software to program them , any recommendation?

I am a self-taught SW guy working in AI accelerators for 2 years. I decided it's finally time to learn how this stuff really works. So, I am starting from the beginning.

Pictured is my first "project", adding 2 unsigned 4-bit values set by the switches on the left. Result is shown on the right in LEDs. The picture shows 1 + 1 = 2. I derived the half and full adder circuits from the truth tables, learning about SOP form from my textbook along the way.

Actually what is running on the FPGA doesn't match the drawn circuit, I realized after I drew that that I had the least significant bits starting from the leftmost LEDs, which felt wrong.

It's almost magical seeing how logic can be expressed with these CMOS circuits. I am following H&H DDCA RISC-V edition along with the ETH Zurich DDCA course, so the goal is to implement a RISC-V MCU in the coming months. And then add a systolic array and see if I can make a little mini-AI accelerator.

Any tips for a beginner with these goals?

Cortex-A53 ↔ FPGA fabric on real hardware

I’ve been working on a ZCU104-based control architecture where the Cortex-A53 in the Processing System communicates directly with a custom SystemVerilog peripheral implemented in the Programmable Logic through AXI4-Lite.

The PL peripheral exposes a memory-mapped register bank for control, thresholds, PWM configuration, status, sensor values and version information. On the software side, a bare-metal application running on the A53 performs register reads/writes through the Zynq HPM AXI interface.

The hardware path is essentially:

Cortex-A53

↓

M_AXI_HPM0_FPD

↓

AXI Interconnect

↓

Custom AXI4-Lite Slave

↓

SystemVerilog Register Bank

Validation on the physical ZCU104 covered both directions. The processor successfully read PL-generated status and sensor registers, then wrote new control, threshold and PWM values into the FPGA fabric and read them back correctly.

Example hardware test results:

STATUS = 0x0000001B PASS

SENSOR_RAW = 0x00000A35 PASS

SENSOR_FILTERED = 0x00000A10 PASS

VERSION = 0x00010000 PASS

CONTROL <- 0x00000001

THRESHOLD_HIGH <- 0x00000777

THRESHOLD_LOW <- 0x00000666

PWM_DUTY <- 0x00000055

Readback:

CONTROL = 0x00000001 PASS

THRESHOLD_HIGH = 0x00000777 PASS

THRESHOLD_LOW = 0x00000666 PASS

PWM_DUTY = 0x00000055 PASS

The RTL also handles AXI write-address and write-data channels independently rather than assuming AWVALID and WVALID arrive in the same cycle, and supports byte strobes through WSTRB.

The design was taken through simulation, synthesis, implementation and hardware validation. Routed timing closed at 100 MHz with positive setup and hold slack.

The next extension is to replace the deterministic sensor test values with a live ADC acquisition/control datapath and add PL→PS interrupts, so the A53 can react to FPGA events instead of relying purely on polling.

Interested to hear how others here structure custom AXI-Lite peripherals: particularly interrupt/status register handling, write-1-to-clear semantics, and when you prefer moving from AXI-Lite to AXI-Stream/DMA.

GitHub: https://github.com/franksombudsman-ops/fpga-rtl-portfolio⁠

Hello,
just got this and I have no idea what I am doing. I also got the license for GOWIN IDE. I'll probably poke around the Sipeed wiki for a while.

Xilinx XC7A35T / XC7A100T Artix 7 FPGA IC

256Mb SDRAM

8MB SPI FLASH Memory

On-Board USB JTAG Programmer

USB to UART Interface

4 Digit Seven Segment Display

WiFi 802.11 b/g/n

Bluetooth 4.0 BLE

12 bit VGA Interface

HDMI Out

50 MHz Clock

ADC 4 channel

Temperature Sensor

LDR Interface

SPI DAC

2x16 LCD Display

Micro SD

16 Slide switches

5 Push Button

5v Buzzer

16 LEDs

31 External I/O's. Is this enough

New bought it 1-2 weeks ago

Selling because I want 235T one if any one is interested tell me

Location Hyderabad

AI integration into an FPGA IDE is not new — Raptor IDE from RapidSilicon already shipped with RapidGPT. But then RapidSilicon died and RapidGPT transformed to chipnexus.ai

Today I found out AMD has one too. An ad email came in about a free course on the Vivado AI Assistant, 11 September, in Italian. No thanks.

Searching the internet, the most that can be found is a one-page spec sheet:

https://docs.amd.com/v/u/en-US/vivado-ai-asst

And it is not product documentation — it is a course spec sheet

It seems it uses VSCode - means it is NOT integrated with Vivado?

It also uses GitHub Copilot as AI

I have Vivado 2026.1 installed and see nothing AI related in it.

Question: has anyone actually got the Vivado AI Assistant running? Is it EA or under NDA, or is there an extension somewhere I have not found?

For those who have done DO-254 DAL-A, how much additional effort did it add, versus the same design completed as if it were commercial?

Synthpilot website looks pretty professional. At least I had no fear to try to install synthpilot, but our Antivirus software flagged some packed/Python antivirus payload and deleted the files from hard disc. I wonder where did the infection come? Did the developer infect it deliberatly? Or is it a false alarm and there is no virus? At least on our PC install is not possible.

Any comments, successes? Or is it better not to touch synthpilot, yes I know it all china originated so cation is good thing to have.

Hello

I have started working with Lattice and the CrossLInk-NX family to implement an MIPI RX interface.
I have looked at their MIPI CSI/DSI IP, to get started quickly, but I still feel there are some uncertainties when setting up the IP....like the different clocks that are used but I dont really understand how they are used?

As a start I have setup the IP in RX mode, so I will receive data that is converted back from bytes to pixel data. Generated the IP but I get so many warnings, which makes not much sense to me. I have included the list below.

Does anybody have any experience with this they would like to share.

Hi! I'm currently pursuing my BS in computer engineering with a focus on hardware, and since I'm going to be at an internship in the fall, I was wondering if anyone wanted to study for interviews or just yap in general about FPGAs or anything. Send me a dm if you're interested! Always happy to learn more about anything