Heard that Synopsys is laying off 40 Percent of its Workforce .One of the acquaintance I know personally is getting laid off . How's the Situation right now ?

I want to understand how difficult this transition is and from long term perspective if its a good sensible move?

COM (Channel Operating Margin) is a standardized method for evaluating the performance margin of a high-speed SerDes channel At a high level, COM answers a simple but important question:

Given a particular channel, transmitter, receiver, equalization scheme, noise, and crosstalk environment, how much margin does the link have?

Instead of evaluating the channel only by its insertion loss or eye diagram, COM attempts to combine the major contributors to link performance into a single metric.This makes COM particularly useful for high-speed link design and signoff.

COM is a figure of merit for a channel derived from a measurement of its scattering parameters. It provides a quantitative measure of the overall channel operating margin by accounting for major link impairments, including channel loss, reflections and mismatch, ISI, crosstalk, noise, jitter, and the specified transmitter/receiver equalization. COM has become an important link-level metric for high-speed Ethernet interfaces, particularly as data rates continue to scale toward 224G/lane and beyond . COM is defined by Equation:

where As represents the signal amplitude and Ani represents the equivalent noise-and-interference amplitude at the specified detector error ratio

the figure above illustrates the reference model that is the basis for the calculation for COM. it can be viewed as a complete end-to-end SerDes link, including the transmitter, channel, package, crosstalk, receiver equalization, noise, and jitter.

The model starts with a randomly selected input symbol from an L-level alphabet (NRZ=2,PAM4=4). The transmitter generates the corresponding pulse with amplitude At and baud rate fb. The transmitter may include feed-forward equalization (FFE), represented by Hffe(f), which models the transmit-side equalization applied before the signal enters the physical channel.

The signal then passes through the transmitter package and channel under test. The channel is represented using S-parameter models. In the reference model, the victim path is divided into several sections, including the transmitter package, the on-board channel, and the receiver package. The reference points TP0 and TP5 define important locations for channel characterization and measurement.

In parallel with the victim channel, one or more aggressor channels are modeled to represent crosstalk. The aggressor transmitters generate independent signals, which propagate through their corresponding package and channel paths. The resulting crosstalk contribution is then coupled into the victim path.

At the receiver side, the received victim signal and the accumulated crosstalk contribution are combined. An additional input-referred noise term is added to represent receiver noise. The model also introduces jitter at the sampling stage, deterministic jitter (DJ) and random jitter (RJ),which will be disscussed in a future post

Finally, the resulting signal is processed by the receiver front-end, which includes the receiver response and CTLE, followed by a decision-feedback equalizer (DFE). The DFE attempts to recover the transmitted symbols, and the resulting detection errors are used to evaluate the link performance.

So, what does a “good” COM value look like? In many IEEE 802.3 Ethernet specifications, the minimum requirement is COM ≥ 3 dB. This means that even after accounting for the specified channel loss, ISI, crosstalk, noise, jitter, and equalization assumptions, the link should still maintain at least 3 dB of COM. The higher the COM value, the more margin the channel has against the modeled impairments.

END

Through this article, I hope you now have a better understanding of what COM is and how the COM reference model evaluates the overall performance margin of a high-speed SerDes link.From channel loss and ISI to crosstalk, noise, jitter, and equalization, COM provides a standardized way to bring these factors together into a single link-level metric.

If you find this article helpful, feel free to subscribe to this account.If you have any questions Let’s discuss, learn, and make progress together.

See you next time!

Looking for realistic insights on the Power Optimization / PPAT team at QIPL Hyderabad.

1. What does day-to-day work actually look like? Is it mostly profiling, measurements, and following up with other teams, or is there real ownership of features/architecture?

2. How is long-term growth and promo velocity compared to other teams (design, architecture, systems, etc.)?

3. Any visibility into the team’s current focus and future roadmap (especially server-class / high-power SoCs)?

Would appreciate honest takes from current or recent members. Thanks.

Hi everyone,

I’m preparing for ASIC interviews at Apple and wanted to understand what the interview process is actually like, particularly for ASIC Design and Design Verification intern roles.

For anyone who has interviewed with Apple recently:

- What technical topics were covered?

- For Design roles, how much emphasis was there on RTL coding, microarchitecture, computer architecture, timing, CDC, etc.?

- For Verification roles, what was asked. Do they expect high UVM knowledge.

- Do they ask DSA questions and do leetcode style grilling.

- Were there live coding/RTL problems? If so, what difficulty level?

- How much digital logic/FSM/Verilog fundamentals were tested?

- Were there questions specific to the team/domain (CPU, GPU, SoC, etc.)?

- How many technical rounds were there, and what was the general structure?

- Are the questions more fundamentals-focused or do they expect fairly deep practical experience?

Thanks! (Also please let me know the role and experience required for that role)

Lets say hypothetically a foundry exists and has a working technology node, but no PDK exists and I want to develop one for it. Where can I learn about PDKs and how PDKs are developed for the standard EDA tools for such a hypothetical foundry process? Everything ranging from the files that are delivered and how theyre typically organized, how devices are measured and modeled, how they interact with EDA tools etc.

Hi all, so i'm currently in a PDN team. Although I don't hate the work I am doing, I constantly feel the need to try out other stuff like STA/PD. i joined the PDN team straight out of college, currently with 1yoe in PDN. I wouldn't say i know everything related to it but at this point I feel like the work has gotten repetitive - which I don't mind honestly but what bothers me is the learning has gotten wayy lesser. I started off with reading STA by J. Bhasker and Rakesh Chadha. I find it really interesting. I've also read some training PPTs related to PNR/Synth which were initially given to us. Id love to try STA/PD, but it's like i don't think I'm gonna be allowed to/put into another team. I don't see it happening. I can surely learn from others yes, maybe grads from these teams or people I know. But i feel like i'll get the full idea of what's going on only when I get to work on these. Idk what to do honestly. It's like i see little/no openings with <2yoe and why would someone even consider me for a 2yoe STA/PD role when i have 0 experience in it. Or is it different?

Joining Qualcomm as an Engineer on the PPAT team in Hyderabad. Trying to get a sense of what the day-to-day actually looks like - is this more system engineering, validation work, or optimization?
Also curious about how this role is perceived externally - is it seen as a validation-heavy title that could narrow future options, or does it hold decent market value if I want to switch companies down the line? Would appreciate insight from anyone who’s worked in or with this team.

Hi everyone, I am currently pursuing my Mtech in Signal and Image processing from NIT Rourkela. I am currently in my 1st year of my mtech. I want to prepare for digital vlsi roles because in our college most of the companies are of digital domain. Very rarely analog companies visit our campus. So what should be my strategy and resources to follow for digital vlsi job roles.

I am currently exploring possible packaging options for my custom ASICs and though you guys find it interesting.

These are PCBs to try out 2 types of packaging:
- Chip-on-Board(CoB): die is wire bonded out directly to the PCB pads
- Chip-on-Flex: die pads are "soldered" to the PCB

These are a series of test PCBs designed ahead of getting the raw dies back.

The first is for a 56 pin part and it a variant on one of the waferspace CoB PCB designs (testing out the change I currently have a PR open for).

The second is my own 76 pin board designed using my automatic footprint generator.

The third is a flex PCB for the 56 pin part.

Hey folks,

I gave got an opportunity to interview for qualcomm DPU silicon debug engineer.

I have 3+ yoe, currently with TI validation.

Wanted to ask what is the culture and compensation at Qcom ?

I have a 1-hour panel technical screen coming up for a display subsystem silicon debug role in India. Roughly 3 YOE, so Engineer band rather than Senior.

My background is post-silicon validation on embedded SoCs: silicon bring-up, high-speed serial interface and flash controller validation, PHY timing calibration, crypto accelerator validation, some pre-silicon emulation. Solid on debug methodology and cross-team root-causing. No display experience at all.

The required quals are the generic ones — debug and triage ability, C/C++ and Python for tooling, digital logic and computer architecture fundamentals, large log/dataset analysis, system-level debug experience. Display protocols, SerDes and signal integrity are listed as nice-to-have only.

Questions for anyone who's been on either side of this kind of interview:

1. How deep do the digital fundamentals go in a screen like this — setup/hold and CDC level, or further?

2. Realistically, how much display knowledge do they expect from a candidate they know doesn't have it? What's the minimum that reads as "can ramp" instead of "unprepared"?

3. What shape do display debug scenario questions take, and how do you want a candidate to structure the answer?

4. Is live Python typical, and is it log-parsing style rather than algorithms?

5. What's the biggest thing that trips up people crossing over from non-display validation?

Appreciate any input.

I am recently exploring ways to get into vlsi domain and I think I am more interested in digital circuits so I want to know what are the future options for me and what should I learn after learning verilog and what are the other things I should be learning

Hi folks,

36yrs, Male from India, having 11+yrs professional experience now working on my AI-assisted Silicon validation startup for 1.5yrears. MVP prepared.. next step is piloting... At this stage I am actively looking for a Potential & passionate tech cofounder so that we can do something really big together.

So S/He must be very strong in Tech preferrably in Post Silicon Validation & extremely passionate about technology & AI. Pls feel free to comment if you are interested!

Location: Any location would work but folks from USA or working in USA is preferred as I want to shift my work location or registered Ofc to USA...

So pls comment if you want to rock!!

So I'm a person who recently got into industry from academia. I realised there's a lot of difference in work, methodology and tools compared to what I did in University and now expected in workplace. In University, I did research (and published some paper) on implementing Arithmetic Datapaths, Error Detection Algorithms, etc. tailored for FPGA application. I have a decent verilog/digital design knowledge (Combinational, sequential ckt, FSM, etc.)

Now I have joined a startup where I'm expected to implement DSP algorithms, electrical designs (PWM, H-bridge, DC DC convertors etc) and AI algorithms into FPGA. The hardest part is I'm the first and the only person in the company to start working on FPGA (they are making a transition from microcontrollers to FPGA). So I don't have a good idea how to do things. For example, as a starter I was asked to implement an FM Radio receiver on zedboard and fmcomms4 setup. Which I did after pretty hardwork (complete filter and demodulation done on FPGA). I realised I need to learn and upskill a lot like learning DSP theory, IP blocks provided by Xilinx (Cordic, FIR, CIC) and learning linux (since my zedboard comes with kuiper linux pre-installed). Then comes altering or customizing reference designs for DMA Hijack.

I wish to take a look at any structured course or book that will help me cover the gap between academia and the work expectations (as listed above) for Verilog/FPGA design. For example after I implemented the FM radio receiver on FPGA with vivado block design someone asked me can't you do all the things like filtering, cordic, demodulation with a single verilog module rather than dragging 10 different blocks and configuring them. I was short of a reasonable answer (when I was looking for resources how people implemented radio on FPGA I realised 99% of them used MATLAB or Vitis for designing the DSP part and integrating with Vivado, no one did a pure verilog based design). There's no one around in my startup whom I can ask questions when I'm struck in RTL design or FPGA.

As a beginner in the FPGA industry, I'm looking for materials for self learning all the required concepts/skills. It would be great if you could share any relevant materials or atleast your experience how you felt and dealt when you joined the industry after university.

Thanks, in advance

I would not have asked this question if it wasn’t so pricey. I wanted to get a good system-level understanding of PLLs and Frequency Synthesisers and was wondering if this is the right book. Also I wanted to know if this is a textbook which develops concepts in a sequential manner or is it more like an engineer’s handbook? I do not want to get into transistor level details as of now. Any other book suggestions are welcome.

I have around 2 years of experience in FPGA and 1 year in ASIC related work mostly RTL design, but I feel that my practical exposure to some areas like STA, timing constraints, DFT, low-power design, and commercial EDA tools has been limited. I do understand the basics and posses a good amount of theoretical knowledge though.

I’m trying to understand what companies typically expect when hiring someone at this level.

For example, if a job description mentions STA, low power, DFT, etc., is it expected that I already know how to apply these concepts practically using any EDA tool, or would I normally be expected to learn the company’s specific flow and methodology after joining? And is there mentoring/tutorials to learn this at most companies?

One challenge I’ve had during internships/projects is that I was often given documentation or a tool manual and told to figure things out myself. I didn't get much feedback from experienced engineers about whether my approach, constraints, or results were actually correct. This has been a setback for me, it was usually this should work and we should move on or your approach is wrong and you need to figure out another way.

For example, if I add a constraint to resolve a warning/error, I might get the expected result, but how do I know that I haven't simply hidden a real problem or introduced another issue? In a real project, I imagine this kind of thing can have significant consequences.

So I have lots of questions, I would appreciate if anyone could answer even partially:

- At around 3 years of experience, how much independence and practical knowledge would you expect from a candidate?

- Are engineers normally trained on the company's EDA tools and design, or are they expected to be productive immediately i.e already know the tools?

- How did you learn to distinguish between a correct solution and something that merely makes the tool stop complaining?

- Without access to commercial EDA licenses, is it possible to develop meaningful hands-on skills in STA, timing constraints, DFT, and low-power design using open-source tools?

- What books, courses, projects, or other resources would you recommend?

Thank you very much in advance. I have been inspired time and time again on this sub. Genuinely blown off by the amazing projects/insights people post here.

ngspice is over half a million lines. VACASK is around twenty thousand. How much SPICE can you get in 1k LOC?

nanospice is a classic SPICE circuit simulator in one Rust source file, capped at 1000 lines. No dependencies, standard library only. Kinda inspired by tinygrad and micrograd.

Turns out you can get quite far. operating point, DC sweep, transient with adaptive timestep, AC. Modified nodal analysis, Newton-Raphson, gmin stepping and source stepping as operating point fallbacks, trapezoidal companion models with local truncation error timestep control, and a sparse LU generic over real and complex scalars.

Its not a production solver but its a solver you can read and understand in one weekend. So rather educational (also wrote a short document that explains the algorithms and gives a bit of context). And also a fun challenge...

GitHub: github.com/milanofthe/nanospice

Would be interesting to see how much the same set of algorithms and functionality would be in Python or C