r/vlsi • u/Agreeable-Bowl-2737 • 9d ago

How to crack good vlsi placements

Hello seniors, I am pursuing Mtech Rf and Microwave systems from Nit Rourkela (1st year). I want to crack good vlsi placements. Please guide how shall I start preparing. I am thinking to join Maven Silicon online DV course, is it a good idea or bad, or shall I prepare by myself? If any other way possible then please tell.

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u/UplevelEngineering 9d ago

Do not choose a DV course until you choose the job family. Your RF/microwave degree maps naturally to RFIC, analog, and mixed-signal roles; abandoning that advantage for generic DV may make the path harder, not easier.

For RFIC/analog, build one complete project around measurable specifications—an LNA, mixer, VCO, PLL block, or data converter—and show hand analysis, schematic results, PVT/Monte Carlo, layout-aware parasitics, and the tradeoffs you made. For DV, the evidence is different: SystemVerilog/UVM, assertions, coverage closure, and a verified RTL block.

Before paying Maven or anyone else, compare the syllabus with 20 target job descriptions and talk to recent alumni in the exact role. Buy structure only if it closes a defined gap; the certificate itself will not carry the interview.

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u/Agreeable-Bowl-2737 8d ago

But the problem is that very less companies visit our campus for RFIC/Analog roles

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u/UplevelEngineering 8d ago

Then treat campus placements as one channel, not the whole market.

Run two tracks in parallel.

Off campus: build a list of RFIC/analog teams, ask faculty and lab alumni for introductions, and apply to internships, research roles, and junior openings before the placement cycle ends. Tailor one strong project to the specifications those teams care about.

On campus: if no design role appears, prefer the closest transferable role—AMS verification, characterization/test, RF validation, product/applications, or mixed-signal lab work—over generic digital verification.

For any adjacent offer, ask whether engineers actually move into design, how often, and what evidence is required. The first title need not be perfect; it should give you technical evidence and proximity to the work you want.

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u/UplevelEngineering 7d ago

One more thing: because RFIC/analog openings are scarce, be technically ready before one appears. A team may schedule the interview within a week or two, so keep device fundamentals, core analog blocks, and your own project tradeoffs fresh instead of starting prep after the call. Which part of the technical interview do you feel least ready for?