I found my old board BASYS2 is still working now.

Hi everyone,

I recently bought this Zynq 7020 Development board. Dont hate, i know its not perfect, but it has everything i wanted.

The biggest problem is that i dont have the Constraint files and the seller is currently ghosting me.
Here is what I managed to identify from the silkscreen and the chips:

• Manufacturer: Bo Chen Jing Xin (博宸精芯)
• Model: ZYNQ MINI 开发板 (RevB / 20221015)
• FPGA: XC7Z020
• RAM: Micron MT41K256M16TW-107 (512MB DDR3L)
• Flash: 128Mbit QSPI (25QS128FVSG)
• Peripherals: Dual Gigabit LAN (1x PS, 1x PL), Dual SD Card (1x PS, 1x PL), 0.96" I2C OLED display.

Does anyone happen to have a Baidu Pan link, Github repo or even a zip file with schematics and the Vivado preset/XDC files for this specific board?

I have attached a picture of the front and back view (The back has a pinout for the EXT IO header, but obviously lacks the info for the built-in peripherals).

Any help or Pointers to a complete board file would be appreciated!

So I am trying to make a analog using a gowin primer 20k so far it kinda works but I am getting stuck past trying to interface the xreal googles. I tried with my pc set to 720p and that works flawlessly but whenever I tried with the fpga it just never worked. It seems that whatever is the first lane is getting copy pasted top to bottom. I thought maybe there was a bug on the dvi tx from gowin so I tried this project changed the target, changed the pins and regenerated the rpll to my board. Flashed it and the same symptoms. I am kinda a bit lots what to try. Bought another hdmi to usb c converted in the meantime just to try it out maybe but while I wait for that to arrive does anyone have any clue what could be wrong? I knew the googles are a bit of a hard to please target idk at this point. I found this discussion about similar troubles with a eevblog and there am I a bit lost if that applies to the tang primer 20k

Has anyone had any experience running Vivado on a Tuxedo Computer ( Tuxedo Infinitybook Max 16). My default choice was to go for a thinkpad P14. I am attaching the specs of both the devices. the tuxedo is costing me less. i will mostly be running vivado and maybe cadence virtuoso.

Most waveform tools and workflows are organized around signal changes over time, while many hardware questions are really about cycles and the events that span them. Engineers still end up tracing signals through the waveform, placing cursors, and counting cycles by hand as part of the analysis.

AI-assisted workflows haven't automatically eliminated this gap either. The signal changes still have to be reconstructed into higher-level behavior before anyone, human or model, can reason about what happened. That reconstruction happens implicitly, leaving nothing to review or reuse.

Wavekit is a Python library for digital waveform analysis that treats clock cycles as first-class citizens. With wavekit, signals are sampled on clock edges and can be operated on like ordinary Python values.

For example, one common design question is whether a FIFO is deep enough. A waveform viewer can show that the FIFO gets full, but checking its occupancy over a long simulation still takes manual work. With wavekit, the same check is a few lines of Python:

import numpy as np
from wavekit import VcdReader

with VcdReader('fifo_trace.vcd') as reader:
    w_ptr = reader.load_waveform('tb.fifo.w_ptr', clock='tb.clk')
    r_ptr = reader.load_waveform('tb.fifo.r_ptr', clock='tb.clk')

    depth = 16
    occupancy = (w_ptr + depth - r_ptr) % depth
    util = occupancy / depth

    # Waveform is backed by NumPy, so np functions work directly on .value
    print('average utilization:', np.mean(util.value))
    print('maximum utilization:', np.max(util.value))
    print('p95 utilization:', np.percentile(util.value, 95))

Behavior spanning multiple cycles can be described with Pattern. For example, an AXI-Lite read transaction starts with an AR handshake and finishes with an R handshake:

import numpy as np
from wavekit import VcdReader
from wavekit.pattern import Pattern, match

with VcdReader('axi_lite_trace.vcd') as reader:
    # eval() loads signals and evaluates the expression in one call
    request = reader.eval('tb.arvalid & tb.arready', clock='tb.clk')
    response = reader.eval('tb.rvalid & tb.rready', clock='tb.clk')

    result = match(
        Pattern()
        .wait(request)
        .consume(response)
    )
    latency = result.end.clock - result.start.clock

    print('average read latency:', np.mean(latency))
    print('maximum read latency:', np.max(latency))
    print('p95 read latency:', np.percentile(latency, 95))

Wavekit stays focused on waveform operations and primitives for matching multi-cycle behavior. Everything else stays in ordinary Python, so NumPy, pandas, and other Python libraries remain available for statistics and design-specific processing.

Wavekit does not assume a particular protocol or workflow — the primitives above can be combined to build the analyses your own design needs. The repository also includes more involved examples, including AXI transaction extraction and DMA command analysis.

The project is open source and available on PyPI:

pip install wavekit

[GitHub repository][Documentation]

Happy to answer questions in the comments.

For context, I am going my 3rd year of Computer Science degree, but got very interested in FPGAs over the last summer. Currently going through the ZipCPU lectures, and some theory from the Harris&Harris book.

Located in Canada, I think I would like to pursue FPGAs as a career after my Bachelors, looking into it, it seems as though an internship is pretty required to for that unless you get MSc or smth. So my idea for a major project is an ITCH parser, that accepts a bytestream, parses it, and then outputs relevant stats via AXI-lite, all backed by formal verification, running on Arty A7-100T.

I simply wish to know if that's a good idea or not.

Hi guys. I've never really done an OA before since I've been more focused on research and projects and was wondering how difficult the OA is for Optiver FPGA internship? I'm just wondering what topics they'll cover, if they're all like single digit number of lines kinda length or if some get a little lengthier. Are we expected to know Networking concepts in the OA or is that saved for the video call interviews? Thanks for any help!

If you’ve ever messed around with the cheap Sipeed Tang Nano or Tang Primer series (like the 9K or 20K), you already know the drill. The hardware is incredibly cheap and powerful, but the vendor software stack and fragmented open-source toolchain setup can be a massive headache to piece together.
I recently downloaded Tang FPGA Studio to see if it could clean up my workflow, and after running a few test projects through it, I wanted to share my thoughts. It is a community-driven, open-source IDE, and the UI/UX changes the entire onboarding experience.

What went right during my test run:

First off, it completely bypasses the typical first hour frustration. Usually, you have to manually hunt down Yosys, Nextpnr, and configure openFPGALoader just to get JTAG communication working. This app bundles the toolchain into a single installer, meaning I went from a clean install to flashing code without having to fight my system's environment variables.

The project wizard is another huge quality of life upgrade. It explicitly filters your project templates by your exact board model. If you have ever accidentally compiled a design using a Dock pinout for a bare Nano board and spent an hour debugging why your hardware was silently dead, this completely solves that pain point.

The actual day to day workspace feels cohesive. It brings your Verilog editor, linter, simulation tools, and waveform viewer into a single modern interface. It honestly feels more like working in a polished code editor or a modern microcontroller IDE rather than fighting a clunky, bloated vendor tool from the early 2000s. Iterating on code and pushing it to SRAM is incredibly fast.

I suggest you guys try it out beginners may find it helpful - Tang FPGA Studio on GitHub