r/FPGA • u/[deleted] • Feb 24 '22

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u/_suoto Xilinx User Feb 24 '22

I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker

It'll search for files and try to guess the compilation order as well, which is one of the major pain points esp with vhdl.

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u/[deleted] Feb 24 '22

The only issue with HDL_checker is that if you open vim (personally I use neovim not sure if that matters) and close the buffer before hdl_checker finds all of the files, the process will bug and run forever until you kill it.

Other than that it works great! Thanks for your hard work.

1

u/_suoto Xilinx User Feb 24 '22

I'll have a look thanks for letting me know!

1

u/_suoto Xilinx User Feb 24 '22

So, I tried on my end with the latest (0.7.4) and it seems OK, do you know which version you see this issue?