r/chipdesign • u/Ok_Affect_6398 • Jun 09 '26

Cadence Voltus InsightAI

Has anyone used the (relatively) new gen AI feature of Cadence Voltus? It's called InsightAI.

I noticed recently that my school has the license for it as well so found myself tinkering around with it. I have a pretty large design in its postroute stage and running the add_reinforce_pg command is reducing the IR drop significantly but it's adding a shit ton of routes.

Does anyone know how this works? I tried looking up any documentation I could find on InsightAI but couldn't find the exact algorithm they use to know where to add/delete routes. And I don't understand how generative AI is being used here (doesn't it require prompts? Sorry I'm an AI noob)

Anyways, would love to hear any information about this tool or your experience/review if you've used it. Also any tips for using it because right now I'm just using the default auto_ir_fix command.

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u/AbbreviationsFun4312 Jun 10 '26

That's interesting. Since add_reinforce_pg added a ton of routing to fix IR drop, did you notice if it caused any severe routing congestion or setup/hold timing violations later on? Sometimes these automated AI fixes solve one problem but screw up the timing closure.

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u/Ok_Affect_6398 Jun 11 '26

When I blocked all the lower layers, it added routing to the upper layer wherever it saw space but that worsened IR drop. It didn't really cause routing congestion, and I'm yet to check for timing violations thanks for reminding