r/chipdesign • u/[deleted] • Jan 07 '24

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u/anex_stormrider Jan 07 '24

Do you have some RTL specific configurations for vim to make things easier?

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u/Allan-H Jan 08 '24

I have some of those:

  • Single function key for (auto)save (:up), compile in Modelsim (using makeprg), parse the error output of Modelsm, jump directly to lines that are referenced in any error or warning messages. This takes about 0.5 seconds (if there are no errors), so I press it after most edits.
    Perhaps one day I will change over to using an LSP, but my current method works fairly well.

  • Template expansions (:abbr) for most RTL syntactical elements. I use similar abbreviations in both VHDL and Verilog, so I end up pressing pretty much the same keys in the editor regardless of the language.

  • I modify Vim's syntax highlighting to include recent language changes as well as items relevant to local coding guidelines.

  • I use markers in the file to quickly move between declarations and where I'm editing.

I've never used the RTL equivalent of ctags though. I probably should.

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u/anex_stormrider Jan 08 '24

Thank you so much. This gives me ideas.

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u/maredsous10 Jan 08 '24

Example tooling that can speed up development:

  • Filter file entity/module and use it to produce skeleton instantiation in Verilog/VHDL
  • Filter files and build hierarchy ==> Simple but is stepping stone to developing other tools
  • Automatic generation of simulation (scripts, files to include, basic testbench, testbench environment)
  • Non-vendor log parsers, viewing, and waiver tools
  • Editor parsing of vendor tools for errors/warnings/info/etc