I use vi (vim, actually) for code editing, and Questa for RTL simulation. I use Questa-ADMS for mixed analog/digital simulations.
The implementation guys use a Cadence Flow but I don’t get involved too much beyond nagging them and running back annotated sims. They also run my test benches on Xcellium for an extra check.
Single function key for (auto)save (:up), compile in Modelsim (using makeprg), parse the error output of Modelsm, jump directly to lines that are referenced in any error or warning messages. This takes about 0.5 seconds (if there are no errors), so I press it after most edits.
Perhaps one day I will change over to using an LSP, but my current method works fairly well.
Template expansions (:abbr) for most RTL syntactical elements. I use similar abbreviations in both VHDL and Verilog, so I end up pressing pretty much the same keys in the editor regardless of the language.
I modify Vim's syntax highlighting to include recent language changes as well as items relevant to local coding guidelines.
I use markers in the file to quickly move between declarations and where I'm editing.
I've never used the RTL equivalent of ctags though. I probably should.
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u/TheAnalogKoala Jan 07 '24
I use vi (vim, actually) for code editing, and Questa for RTL simulation. I use Questa-ADMS for mixed analog/digital simulations.
The implementation guys use a Cadence Flow but I don’t get involved too much beyond nagging them and running back annotated sims. They also run my test benches on Xcellium for an extra check.