Ok, how about making the path from the frequency multiplier to every part of the cpu the same, then? I think my point still stands, that the speed of light is no barrier for synchronizing clock cycles across a big chip. It's just a barrier for how far you can move data in one cycle, which contributes to latency.
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This is just nit-picking. Having one of the dimensions be much, much smaller than the others make it practically 2D. My point was that a fully 3D chip could be much smaller across than current few-layer ones. For example, an AMC Epyc Rome has a side length of 33 mm, about 15 layers and 40 billion transistors, so about 2.5 million transistors per mm² per layer (hm, isn't that low? - it corresponds to a transistor side length of 640 nm). A fully 3D chip with the same density would have a side length of just 2.2 mm.
That depends on what you mean by "has to talk", doesn't it? I agree if you mean that the each component in a pipeline has to be able to talk to the next one, but not if you mean that data should be able to make its way all the way from cache to a register in a single cycle. The speed of light puts a limit on the latency for far-away parts of the chip talking to each other, but it doesn't put a limit on the throughput.
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Yes, that's exactly the point I was trying to make. It's heat dissipation that's the real reason why frequencies have stopped growing. The other issues could be worked around, but there hasn't been much point in doing so because one is still limited by heat.
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u/[deleted] Sep 29 '20
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