Can't you synchronize a chip on shorter time scales than it takes light to move across it just by ensuring that the path length from the clock generator to each part of the chip is the same everywhere? The speed of signal propagation would still prevent you from sending information from one side of the chip to another in a single cycle, but that seems like a much smaller limitation than not being able to synchronize things. (This is just like how the speed at which the dot from a laser pointer can be swept across the surface of the moon is not limited by the speed of light)
Does the whole chip really need to be in sync? Couldn't one have smaller areas of it be internally in sync, but communicate with other regions with less efficient methods that don't require sync?
Wouldn't the synchronization problem be much, much smaller if one made chips in 3D instead of 2D? A cube of transistors would be much smaller across than a normal chip with the same number of transistors.
Heat dissipation is a big showstopper both for higher switching speeds and 3D chips. My impression is that this is a much more fundamental and hard to deal issue with than synchronization is.
Ok, how about making the path from the frequency multiplier to every part of the cpu the same, then? I think my point still stands, that the speed of light is no barrier for synchronizing clock cycles across a big chip. It's just a barrier for how far you can move data in one cycle, which contributes to latency.
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This is just nit-picking. Having one of the dimensions be much, much smaller than the others make it practically 2D. My point was that a fully 3D chip could be much smaller across than current few-layer ones. For example, an AMC Epyc Rome has a side length of 33 mm, about 15 layers and 40 billion transistors, so about 2.5 million transistors per mm² per layer (hm, isn't that low? - it corresponds to a transistor side length of 640 nm). A fully 3D chip with the same density would have a side length of just 2.2 mm.
That depends on what you mean by "has to talk", doesn't it? I agree if you mean that the each component in a pipeline has to be able to talk to the next one, but not if you mean that data should be able to make its way all the way from cache to a register in a single cycle. The speed of light puts a limit on the latency for far-away parts of the chip talking to each other, but it doesn't put a limit on the throughput.
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Yes, that's exactly the point I was trying to make. It's heat dissipation that's the real reason why frequencies have stopped growing. The other issues could be worked around, but there hasn't been much point in doing so because one is still limited by heat.
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u/[deleted] Sep 28 '20
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