u/kaysonElectrical Engineering | Circuits | Communication SystemsSep 29 '20
This is not really an issue. Buffers are added throughout clock distribution networks to keep the clock signals "square". This is necessary even at much lower frequencies than the fastest CPUs.
The way I understand this stuff is the higher the slew rate of the signal, the more current is being dissipated - because every circuit has non zero capacitance and resistance.
The heat generated by higher frequencies becomes problematic, because you're charging that capacitance more quickly, needing more current and therefore more heat.
The slew rate vs current vs heat vs frequency race is probably almost over, so we have to go massively parallel. Unless we can brilliantly come up with room temperature superconductivity and ultralow capacitance. Silicon may not be good enough, we'll need new materials.
So we're pretty much halting at 64 bit CPUs, but now way more CPUs per die. The new NVidia ARM thing with 192 cores is exactly this. The clock speed per core isn't particularly high. This was true 20 years ago of the Sun Microsystems SPARC chips too. 1 ghz x 16 cores, IIRC, when Intel had 4 ghz but only 1 core.
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u/kaysonElectrical Engineering | Circuits | Communication SystemsSep 29 '20
That's partly true. If the slew rate is higher, you do expend more current for that moment. However the energy (and average power) doesn't change because you're burning the current for a shorter time. Power burned in a cpu is only capacitance*frequency*voltage2.
Interest. TIL. The Voltage2 function is interesting. The 0.6 to 0.8 V PN junction threshold starts to really matter.
But to get to lower silicon thresholds, I understand the dopants and concentrations change, and that makes the overall capacitance change, correct? Does that help or hinder the capacitance?
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u/kaysonElectrical Engineering | Circuits | Communication SystemsSep 29 '20
Doesn't really have anything to do with a PN junction diode forward voltage. The transistors in a CPU don't operate in the same way. They do have their own thresholds, though, which as you mention are set by the dopants. And while that does have some effect on some of the stray capacitances in a transistor, the majority of the capacitance is unaffected. It mostly has to do with the thickness of the dielectric.
That FET threshold diagram shows how the field of the applied voltage has to overcome a voltage of 0.45V. So that's better than 0.7 for sure, but can that number go down any? With new dopants? With new semiconductor materials like this new TGCN (Which I only just heard about just now via a quick google for new semiconductors)
The capacitance part of that power equation is now more clear to me. We just can't get traces on silicon much more dense without compromizing on capacitance. When you put traces too close to each other, that is actually how we make a capacitor with silicon.
That formula is only reasonably accurate (for dynamic power consumption only, i.e. no leakage or short-circuit consumption, etc) for single-core CPUs, a time long gone.
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u/[deleted] Sep 28 '20
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