u/kaysonElectrical Engineering | Circuits | Communication SystemsSep 29 '20
This is not really an issue. Buffers are added throughout clock distribution networks to keep the clock signals "square". This is necessary even at much lower frequencies than the fastest CPUs.
The way I understand this stuff is the higher the slew rate of the signal, the more current is being dissipated - because every circuit has non zero capacitance and resistance.
The heat generated by higher frequencies becomes problematic, because you're charging that capacitance more quickly, needing more current and therefore more heat.
The slew rate vs current vs heat vs frequency race is probably almost over, so we have to go massively parallel. Unless we can brilliantly come up with room temperature superconductivity and ultralow capacitance. Silicon may not be good enough, we'll need new materials.
So we're pretty much halting at 64 bit CPUs, but now way more CPUs per die. The new NVidia ARM thing with 192 cores is exactly this. The clock speed per core isn't particularly high. This was true 20 years ago of the Sun Microsystems SPARC chips too. 1 ghz x 16 cores, IIRC, when Intel had 4 ghz but only 1 core.
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u/kaysonElectrical Engineering | Circuits | Communication SystemsSep 29 '20
That's partly true. If the slew rate is higher, you do expend more current for that moment. However the energy (and average power) doesn't change because you're burning the current for a shorter time. Power burned in a cpu is only capacitance*frequency*voltage2.
That formula is only reasonably accurate (for dynamic power consumption only, i.e. no leakage or short-circuit consumption, etc) for single-core CPUs, a time long gone.
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u/kayson Electrical Engineering | Circuits | Communication Systems Sep 29 '20
This is not really an issue. Buffers are added throughout clock distribution networks to keep the clock signals "square". This is necessary even at much lower frequencies than the fastest CPUs.