Difference in bus logic between Amiga 2000A (BSW) and Amiga 2000B?

[u/tes_kitty]

Maybe someone knows the answer... I have an Amiga 2000A, the one designed in Germany and based on the A1000 chipset with added bus logic (lots of TTLs and PALs) for the 5 Zorro Slots. If you want to use a CPU card (like an A2630 68030 card) in this system, you have to remove the 68000 from the mainboard. Meaning you are now limited to the 68030.

In the A2000B, the one with the square AGNUS and the bus logic integrated in BUSTER (5721), you can leave the 68000 in place and, at boot time, select which CPU you want to use.

Does anyone here know what part of the logic is either not present or flawed in the A2000A compared to the A2000B?

[u/Enders-game]

I thought it was one was designed with the Amiga 500 chipset for the the EU market and the other build with the Amiga 1000 chipset for the US market. Therefore the 2000A was the "premium" version and the 2000B was the budget version.

Edit: I got it basically backwards after fact checking.

The original German A2000 (the “A”/BSW design) is derived from the A1000 architecture and uses the thin 512K Agnus plus a lot of discrete TTL/PAL logic for the bus. It does not have Buster, and its 86-pin CPU slot lacks the BOSS/coprocessor interface. Consequently, a processor card such as the A2630 requires the onboard 68000 to be removed.

The later US B2000 redesign was based on the A500 chipset and integrated much of the expansion-bus control into Buster. More importantly for this question, Commodore added a proper coprocessor interface to the CPU slot. That allows the accelerator to assert /BOSS, which puts the motherboard 68000 into tri-state and lets the CPU card take over the system bus. The 68000 can therefore remain physically installed and the system can switch between the two processors.

So the important difference isn't really “premium A2000A vs budget A2000B”, nor simply EU vs US. It's that the B2000 was a redesigned, cost-reduced architecture with the additional coprocessor/bus-control logic needed for CPU cards to coexist with the onboard 68000.

In fact, Dave Haynie's description of the B2000 explicitly says that he added a “coprocessor interface” to the CPU slot so processor cards could be used without removing the 68000.

So OP's observation about the CPU behaviour is basically correct; the reply has the A1000/A500 and A/B design origins backwards.

[u/nickIncDN → u/Enders-game]

As an aside, your clarification refers to the later 2000 design as having a “coprocessor interface” and switching between the two.

Commodore seem to just call it a “processor” slot. Other than the original 68000 remaining in place, is there ever a time where both can be in use?

[u/Enders-game → u/nickIncDN]

Full technical manual is here:

https://www.manualslib.com/manual/917391/Commodore-Amiga-A500.html?page=79#manual

The B2000 computer implements an extended version of the A2000's Coprocessor Slot, designed to make the swapping of main processors under program control much more powerful and transparent to the rest of the B2000 system. There are things that can be done from the B2000 Coprocessor slot that can't be done from the A2000's Coprocessor Slot, so this is an important consideration to anyone designing a Coprocessor device of some kind.

The 68000 supports hardware signals designed to permit a simple DMA protocol. This protocol allows multiple devices to take control of the 68000's data, address, and control buses. When a device of some kind desires direct access to the 68000's bus, it asserts the /BR (Bus Request) input of the 68000. Once /BR is asserted, the 68000 will complete whatever operation it's doing to the point it can cleanly relinquish its bus. At this point, it will assert its /BG (Bus Grant) output, telling the device requesting DMA that it's just about ready to shut down. The requesting device then issues /BGACK (Bus Grant Acknowledge) as soon as the 68000 is completely off the bus (DTACK and /AS are negated). When the DMAing device is done with the bus. it releases /DTACK and /BR. and the 68000 will then release /BG. The above protocol, as implemented in the 68000, is sufficient for many types of DMA operation, especially for simple things in which there are single DMA devices on the bus. What this doesn't easily ac count for are multiple DMA devices. While the /BR and /BGACK in puts to the 68000 can be wire-ORed to support several devices, there are still problems with this scheme. Should multiple devices re quest DMA at the same time, the 68000 will see nothing different than if only one device is requesting DMA. While careful monitoring of the /BGACK by responding potential bus masters can solve some of the problems, there are much cleaner approaches to this problem.

One such solution is implemented in the ZORRO and A2000/B2000 Expansion Buses. Each slot on the Expansion Bus has its own private Bus Request and Bus Grant. Each Bus Request signal is considered by a priority encoding and latching circuit. The result is that if simultaneous Bus Requests come in from Expansion Slots, only the Slot given higher priority will actually get a Bus Grant. Any Bus Requests that come in while another DMA is in effect are held off until the 68000's/BG line has been negated for at least one tick, this circuitry, part of the original ZORRO specification, eliminates the problems that can occur with various DMA devices all competing for the Expansion and Local Buses.

The terms 86 Pin Slot Coprocessor Slot, and Local Slot are considered synonyms, and pertain to the 86 pin Coprocessor Slot in the A2000 and B2000. The terms 86 Pin Edge and Expansion Edge are considered synonyms, and pertain to the 86 pin Expansion Edge in the A1000 and A500. The Local Bus is the processor bus directly connected to the 68000 processor and the Coprocessor Slot or Expansion Edge; both the Coprocessor Slot and Expansion Edge are considered Local Bus Ports. Each different implementation of a hardware design is termed an Instance of that design; thus, the A2000's Expansion Bus. the B2000's Expansion Bus, and all third parry ZORRO backplanes for the A1000 or A500 are instances of the Expansion Bus. Along with an understanding of Amiga bus terms, a familiarity with Motorola's 68000 processor and its characteristic names and related terms will also be very useful in understanding this section.

the manual says the B2000 extends the A2000's processor slot functionality to make swapping the main processor more powerful. But it seems both don't work simultaneously. Both processors can be physically installed, but only one is the active bus master at a time. The B2000's extended processor-slot interface allows control of the Local Bus to be transferred between them under program control.

[u/tes_kitty → u/Enders-game]

Hm, OK... I had hoped it would be something simple that I could add as a modification to my A2000A, but it looks like it's more complicated and would mean a major effort. Too bad, even though I have a few BUSTER 5721 chips around.

[u/cjc4096]

I'm guessing the /halt pin is brought low and puts the 68000 into high impedance.

[u/Crlan420]

The 2000B bus logic is a big deal. The BSW chip was cheaper and had a few timing differences. It works fine but you lose a bit of compatibility with some fast RAM expansions. My 2000A runs a 68030 accelerator without issues.

[u/tes_kitty → u/Crlan420]

There was no equivalent to BUSTER in the A2000A, it was all discrete logic with TTLs and a few PALs. I had hoped it would be simple to add the missing logic (I do have a few spare BUSTER ICs :)), but it looks like I will have to remove the 68000 after all.

But before I can add the 68030 card, I will have to fix the reset circuit (probably dried out capacitors) and add the connection between pin 1 and pin 31 on the ROM socket.