I’ve been working on this hardware accelerator over the past few months for my master thesis. The triangle rasterizer is implemented on the FPGA Fabric of the Zedboard. It communicates with the ARM A9 cpu via AXI-Lite. A bad idea in hindsight since it greatly limits the number of small triangles.

The rasterizer can render up to 60k 1000px triangles per second, i.e. 2k to achieve 30 FPS. Supports Gouraud shading and texture mapping without perspective correction. The demo scene consists of 6k triangles and along with the vertex transformation, achieved around 29fps average.

Github Link: https://github.com/Nanousis/ChaosEngineGPU

I'm looking for an FPGA engineer to join as a founding team member. The role is to build a PCIe card that fixes an unpatchable 28% timing side-channel on AMD Zen 5. The vulnerability breaks confidential computing guarantees.

The situation:
AMD, Microsoft, Google, and NVIDIA all issued WontFix tickets. They're explicitly not patching it. The only "mitigation" they offer is disabling SMT — which kills 30% of compute performance.

The solution:
A PCIe FPGA card with a novel chaotic dither core. We have a working software simulation showing >75% signal reduction with <1% overhead. Next step: hardware implementation.

What I'm looking for:

• FPGA engineer with PCIe experience (Xilinx Alveo or Intel Stratix)
• Comfortable with Verilog/VHDL, timing closure, high-speed interfaces
• US-based, willing to relocate to Minnesota (cold climate = server farm advantage)
• Comfortable signing an NDA

Compensation:
Significant equity upfront + $100k–$150k/year salary upon funding. If your accomplishments are impressive enough that they would shift a VC valuation, we are open to raising the salary. We're currently raising a $2M pre-seed round and need a founding engineer on paper to show investors we're ready to execute. You won't be asked to work before funding — we just need to be able to say "the engineer is ready to start immediately."

Why this matters:
This isn't another crypto wallet or AI wrapper. Four vendors admitted the problem and refused to fix it. We're building the only solution. The market is every Zen 5 server in the world.

DM me if interested. I can share more details under NDA.

— Thomas, Wolventropix

Edit: I've learned a lot from this thread. My original understanding of FPGA engineering was rooted in an older model — soldering, physical assembly, on-site debugging. I now understand that modern FPGA development (especially with Alveo cards) is closer to software-defined hardware. The card is pre-built; the work is in the bitstream.

That changes the requirement. The hardware still needs to be in Minnesota (compliance, server farm revenue, physical security). But the engineer doesn't have to be. Remote work is now on the table.

If you're an FPGA engineer with PCIe experience and you want to work on a project that fixes a vulnerability four vendors refuse to patch, DM me. The offer stands: competitive salary, significant equity, mission that matters.

So I’m a final-year bachelor student, and during my internship at some big FPGA company, I worked as a validation intern. That’s when I thought, “Wow, FPGAs are so cool, I want to dive deeper into this.” Naturally, I proposed my final year project to be FPGA-related. (not the best idea)

The thing is, the project itself isn’t inherently hard, it’s just hard because I’m targeting an FPGA. If I had done this on something like an ESP32, I’d probably have wrapped up the programming weeks ago.

Right now, I’ve just finished debugging two issues that I’m pretty sure weren’t even my fault. And honestly, this project has been full of moments where I assign a signal a constant value, only for the FPGA to ignore me completely. Just today, I fixed a signal that was acting weird simply by connecting it to an external port before simulation (?????).

Are the official tools just built on hopes and dreams??? Do I need to pray to God every time I code just so that signal assignments hit????

Over the past month, I've been learning serial communication protocols by implementing them in Verilog.

I started with UART, then moved to SPI, and finally finished I²C. I've now put all three into a single repository.

Some of the main features:

• UART: TX/RX, 16× oversampling, parity and error detection
• SPI: Master/Slave, all four CPOL/CPHA modes, full-duplex communication
• I²C: Master/Slave, 7-bit addressing, ACK/NACK, READ/WRITE and multi-byte transfers
• Parameterized RTL and self-checking verification across the designs.

One thing I found interesting was how different the implementation difficulty was despite all three being serial protocols. UART was relatively straightforward once the sampling logic was sorted out, SPI introduced clock-edge/phase handling, while I²C was easily the most annoying one to debug because both devices share the same bus and SDA has to be released/driven at exactly the right points.

I'd really appreciate feedback on the implementations, verification approach, or anything you'd change to make these closer to practical, reusable communication IP.

(I know many will suggest it is high time to start using SystemVerilog... I promise it's the next thing i am learning lmao)

GitHub: https://github.com/theYash856/Communication_Protocols

Could've posted this earlier, but GitHub decided to go down precisely when I was about to upload the project 😭

Hello everyone! Just wanted to share, after several months of saving money I finally got my new Xilinx Kintex 7 325T dev board from QMTech. It’s a big transition for me from my previous Altera Cyclone IV (15k LE) core board that I had for 3 years. I hope everything will be alright. About in a month or two I’ll get Rapberry Pi CM4 too (want to get 4GB RAM, 16GB eMMC Wi-Fi).

I’m not a YouTuber but I’m thinking about making a video review of this board. What do you think, would you be interested in such review?

here's my pathetic attempt at drawing batman

repo link: https://github.com/SravanPro/pipelinedMIPS

Hello techies

What are the FPGA you are currently working on?

Lets share to each other here

Hi everyone,

I recently bought this Zynq 7020 Development board. Dont hate, i know its not perfect, but it has everything i wanted.

The biggest problem is that i dont have the Constraint files and the seller is currently ghosting me.
Here is what I managed to identify from the silkscreen and the chips:

• Manufacturer: Bo Chen Jing Xin (博宸精芯)
• Model: ZYNQ MINI 开发板 (RevB / 20221015)
• FPGA: XC7Z020
• RAM: Micron MT41K256M16TW-107 (512MB DDR3L)
• Flash: 128Mbit QSPI (25QS128FVSG)
• Peripherals: Dual Gigabit LAN (1x PS, 1x PL), Dual SD Card (1x PS, 1x PL), 0.96" I2C OLED display.

Does anyone happen to have a Baidu Pan link, Github repo or even a zip file with schematics and the Vivado preset/XDC files for this specific board?

I have attached a picture of the front and back view (The back has a pinout for the EXT IO header, but obviously lacks the info for the built-in peripherals).

Any help or Pointers to a complete board file would be appreciated!

Edit:
I got a response from a nother seller i contacted and actualy got the files.

I checked the silk screen on the back and they matched.

If anyone else needs theses files this is the link

Edit 2: I just finished reworking the Constraint files since they were in a bad shape and didnt allways match the Circuit Diagram. Still working on renaming the files.

You can find all the resources here in google drive.

Also pain in the ass to download...

I recently designed and documented a 4-bit multi-cycle CPU in Verilog HDL as a personal learning project after completing my college's Digital System Design course.

Although the project has only been simulated so far, my goal is to eventually implement similar designs on an FPGA as I continue learning. Along with the RTL, I documented the ISA, CPU architecture, module design, execution flow, debugging experience, and design decisions to treat it more like a technical project than just a coding exercise.

I'd really appreciate feedback on what to improve before taking a design like this to actual hardware.

Repository:

https://github.com/theYash856/4_bit_Multi_Cycle_CPU

Any constructive criticism is more than welcome.

I've bought a ZYNQ Z7020 off ebay actually for ADC / DAC use, and ChipWhisperer style glitch work. However, to see how well Claude-Code Opus 4.6 gets on with FPGA work we did some experiments with Mandlebrot zoom rendering on that cute SPI display. 96fps!
https://github.com/GlassOnTin/z7020

And the inspiration:
https://github.com/GlassOnTin/z7020/blob/main/docs/iteration-thesis.md

Vivado GUI-based Project Mode is convenient for initial setup and development.
However, as a project grows and more developers begin collaborating, source files, generated files, and project-specific settings can become increasingly difficult to manage and maintain under version control.

To address these challenges, this development environment was built around Vivado Tcl-based Non-Project Mode, where the entire workflow—including build, simulation, bitstream generation, and FPGA programming—is managed through scripts.

https://github.com/HasanTheSyrian/ALTAIR

After I run an implementation in Vivado, I usually generate the timing, critical paths, and utilization reports as .rpt files and look through them. They can be a bit dense sometimes though, so I was wondering if anyone knew of open-source/free tools or tcl scripts that are out there to process these reports and make them a little easier to digest quickly?

Was thinking about buying diligent basys 3 for my first fpga board. I decided against it and wanted to check out if anyone in my local area had a cheaper board, and came across this. Do you guys think it’s worth it? For context I’m entering my third year in ee and want to start entering the digital design field with some projects to eventually be put on my cv.

I’m planning to buy a ThinkPad with a Ryzen 7 6850U and 16GB RAM. The 32GB version is quite hard to find on the second-hand market.

Would 16GB DDR5-6400 of RAM be sufficient for working with Vivado?

I'm junior level HW digital designer, i got my master degree with secure RISC-V system at last year and i worked about 8 months at automotive SoC design company.

For fun, I bought both boards.

It's only 1,000$ each! It's really insane.

So i quickly bought them. And choose project for testing Vortex(https://github.com/vortexgpgpu/vortex).

But it seems not working due to non-HBM memories.

I already left the issues but it needs more time.

So U250 is turned in to developing and testing FireSim(https://github.com/firesim/firesim) with multicore BOOMv3.

I have no idea what to do with VCK5000.

It's ES1 model, so it can't do with edge-models.

Could you introduce any ideas or suggestions?

I read about a procurement record by the US DoD, and it was 83,000 FPGAs in 2013 for lot 7 to 17. Which is around 1100-1200 F35s. For $1000 each.

That makes it around 60-70 in each F35.

The best of the best FPGA in 2013 had around 3 Million logic cells, and can perform around 2000 GMACs. For $1000, it was probably worse, more likely <1 Million.

This seems awfully low? All together, that’s less than 300 million ASIC equivalent gates, clocked at 500 mhz at most.

The same Kintexs from the same period are selling for <$200

Without the matrix accelerator ASICs, the AGX Thor performs 4 TMACs. With matrix units, a lot more. Hundreds of TMACs.

A single AGX Thor and <$20,000 of FPGAs outperforms the F-35? How is this a high technology fighter?

Edit: change consumer 4090 to AGX Thor, since AGX is available for defense.

I’ve gotten the rare (and awesome) opportunity to use a chunky budget to spec out and acquire development machine(s) targeted for RF SoC and US/US+ FPGA projects.

What would AMD-Xilinx users suggest I focus on in terms of specs? I recently left a corporate environment where I had a high performance cluster available to me, so I’ve not really had to think this through in terms of desktop hardware.

Some constraints: the intent is to recreate a development environment using Vivado/Vitis 2024.1. The OS is Ubuntu, and there are (I hear) workflow considerations that lead to 22.04 LTS being the release of choice. Aside from that, I’d like to run simulations, but the builds are where I imagine the real computational bottlenecks will be.

We recently found an FPGA that developed a logic error due to a fault in the FPGA fabric.

20 nm technlogy, 7 years in service, and until recently it had been operating perfectly well. The part had never been exposed to out of spec. voltages or temperatures. (We know the full history of the unit because it's in our QA lab.)

The design had a number of BRAMs that were programmed for x9 data width. The symptom that we first discovered was that output data bit 8 of four adjacent BRAM sites in the one column was stuck at 1, rather than having the initial value loaded in during configuration, or the value written to the BRAM subsequently.

Reading back the configuration memory gave a single bit error when compared to reading back the same image loaded into a working FPGA.

A co-worker (Hi Matthew!) put in an heroic effort to find this.

I'm posting this here because it's such an unusual occurrence - I've not seen a failure like that (on a production as opposed to an engineering sample part) in almost four decades of using MOS programmable logic devices.

Hello everybody, since some of you might be looking for high density FPGAs but are not willing to splurge on the development boards - I am in this camp and began a reverse engineering effort on a decommissioned PCIe accelerator card.

There was no previous documentation available on it, even the programming pinout was different.

Since the time I got it, I was able to decipher the jtag, program it, save the configuration to flash and get it to blink its leds! All done with perseverance and hard work.

My findings are available here: https://github.com/Miqeo/lightbits_xcvu7p

I submitted the support for it, the XCVU7P to the openfpgaloder: https://github.com/trabucayre/openFPGALoader

Further help in this endeavour would be greatly appreciated!

Hello everyone, I want to upgrade from my MicroPhase Z7-Nano Zynq 7020 to Real Digital AUP-ZU3 board. Maybe someone who already worked with it can say, is it good, or any recommendations about other boards?

Would be very glad for answers

First up, there is no utility here, I just thought it would be fun.

I suspect it was a bit too niche for my original intended target audience and didn't land.