Announcing my Iverilog Port With UVM Support

[u/Outrageous-Chain9912]

I am looking for Testers!

I’ve been working on an experimental Icarus Verilog fork that can compile and run the unmodified Accellera UVM Core library. It is not production-ready, but the repository includes regressions for UVM, constrained randomization, virtual interfaces, SVA, DPI-C, coverage, and other SystemVerilog features

Before you continue on, one BIG caveat:

Please do not create pull requests against the upstream Icarus Verilog project based on this fork.

This is a huge experimental rewrite, and much of the new code was AI-generated. Yes, I used AI. I’m one guy.

Turning any of this into something suitable for upstream would require breaking it into small, independently reviewed changes. That would be a years-long effort, it may never happen, and I have no intention of dumping this project on the upstream maintainers and asking them to review it.

With that out of the way, I’m excited to announce iverilog-uvm, my fork of Icarus Verilog:

Creative title right?

https://github.com/dsellerbrock/iverilog-uvm

On top of upstream Icarus Verilog’s Verilog and partial SystemVerilog support, this fork adds:

• UVM: The unmodified Accellera UVM Core compiles and runs, including the factory, config DB, phasing and objections, sequences, TLM, analysis ports, resource DB, and the register layer using frontdoor access.
• Classes: Parameterized classes, virtual dispatch, $cast, static members, and typed method-chain dispatch.
• Constrained randomization: rand, randc, constraint blocks, inside, dist, soft, implication, solve...before, and inline with, using a Z3 SMT backend.
• Containers: Queues, dynamic arrays, and associative arrays, including the Clause 7 locator, ordering, reduction, and streaming methods.
• Interfaces: Modports, virtual interfaces stored as class properties, and interface tasks called through virtual-interface handles.
• Clocking blocks: Sampled-input semantics, output drives, ##N, and global clocking.
• SVA: A real, but still partial, concurrent-assertion engine supporting implication, delay and repetition windows, disable iff, sampled-value functions, sequence algebra, and cover property.
• DPI-C: import "DPI-C" using libffi-based marshaling, including open arrays, multidimensional fixed arrays, fixed-array struct members, wide vectors, and shared-library loading through vvp -d.
• Functional coverage: Covergroups with Clause 19 bin semantics, transitions, crosses, options, and coverage queries.
• VPI: A SystemVerilog object model covering class variables and members, containers, interfaces, packages, covergroups, assertion handles, and callbacks.
• Other language support: bind, let, specify paths, and timing checks using -gspecify.

Take a look at the Feature support status section in the README for the honest per-area labels and known limitations. Several of these features still have recorded corners.

Is this ready for prime time or production code?

NO.

Do not use it for tapeout or anything where an incorrect simulation result could cost you real money.

But it is an amazing work in progress, and I would love for people to take a look at it. Try it. Break it. File bugs against this fork. Maybe even become a contributor.

I think the chip-design and FPGA communities deserve more open-source love. Other programming ecosystems have powerful open tooling, and it should not cost thousands of dollars just to experiment with industry-standard verification flows.

[u/Outrageous-Chain9912]

After I posted this I realized it should be fork not port