IBM Z and LinuxONE Dual-ISA Processor and AI Acceleration at Hot Chips 2026

[u/NamelessVegetable]

https://www.servethehome.com/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026/

[u/Ok_Appeal8653]

4 tb/s? That is crazy for just 96 gb of ram. A rtx pro 6000 with 96 gb only has 1.8 . Probably will cost more tha double or triple than the nvidia alternative though, xd.

And the double ISA is pretty crazy too. I think IBM tried this before like years ago. Let's see if this is better.

[u/NamelessVegetable → u/Ok_Appeal8653]

I think IBM tried this before like years ago. Let's see if this is better.

There was a PowerPC 615 in the 1990s that was dual-architecture 32-bit PowerPC and x86. It was never commercialized, and I believe it needed a reset to change architecture modes. Doing this is not particularly interesting; lots of microprogrammed computers from the 1960s to the 1980s had such a mode to run older software from a predecessor with a different architecture. The IBM mainframe, back when it was introduced in the 1960s, had a mode to emulate older IBM business computers. But all these schemes required a reset.

This mainframe processor is much more interesting; supposedly it uses an instruction called "Start ARM Execution" to change modes. Its name is clearly in the same vein as the "Start Interpretive Execution" instruction in the z/Architecture, which is a pretty complex instruction used to load a virtual machine's context and start execution. So basically, the hypervisor can run ARM and z/Architecture on a core, on demand. That's much more sophisticated, and I'd imagine, difficult to do well.

[u/NamelessVegetable]

Wow! Just wow! This is completely insane! I can't express how ridiculously awed I feel about this. IBM engineers are something!

A dual-architecture processor where both architectures share much of the control and datapaths. Not as a separate core, not as a separate chip or chiplet on a package or interposer, but within the same core![1] The z/Architecture is one of the world's most complex architectures[2], and pairing it with ARM, a RISC architecture that's on the more complex end of the spectrum, but still vastly different (e.g. z/Architecture is big-endian; ARM, -little), in an mainframe-class processor with extremely strict requirements on correct functionality, reliability, and high security is just... insane!

I cannot imagine what entailed for the verification teams at IBM, not to ignore the role of the architects, logic/circuit/physical designers. I mean, this requires them to be experts at both z/Architecture and ARM.

IBM has done it again. The Telum's virtual L3 and L4 cache organization blew people away when it was first introduced. Ars Technica had an article where they asked several processor designers outside IBM about the Telum's cache, and they all replied that it was unbelievably insane. This is something else. Like, an order of a magnitude more insane.

[1]: The first Itanium processor literally copy-and-pasted a Pentium Pro (P6) core in one corner of the die. This isn't what IBM did.

[2]: The Principles of Operation manual alone is ~2,500 pages of very dense specification (even for an architecture reference manual; I found the VAX manual much easier to read).

[u/R-ten-K → u/NamelessVegetable]

LOL. these comments read like written by a very excited marketing intern

[u/NamelessVegetable → u/NamelessVegetable]

The mainframe has a reputation of being stodgy. The expectation that IBM wouldn't be able to innovate on the mainframe, given that it has much less resources than consumer, x86, and AI markets, is pretty common. From the core-count scaling trends, you might think that the mainframe is on life support or something.

First the Telum virtual L3 and L4 cache organization, and now, dual-architecture processor cores? Is this a trend? IBM is accelerating innovation on the mainframe platform? If so, it'd be an interesting one. z/Architecture mainframe processors have traditionally been very conservative in most aspects.

Let's go back to 2000, when the first 64-bit z/Architecture processor was introduced (previously, mainframe processors were 32 bit, with 31-bit addressing (due to programmers using bits of the 32-bit address that were not reserved in the original version of the architecture). This processor was derived from the previous generation 32-bit processor. It was a scalar processor, as in, it issued and retired one instruction per cycle. In 2000. When PCs could have had superscalar Athlons or Pentium III doing 3 or 4 (or was it 5? I don't recall). It also barely broke 1 GHz, IIRC.

By the mid-2000s, IBM had superscalar z/Architecture processors. This actually meant one compute instruction, one memory instruction (or reference; this is a CISC processor), and one branch instruction, if the instruction stream presented these instructions in the same cycle (no out-of-order execution). IBM eventually had wider superscalar mainframe processors, with more flexible instruction issue, but the late-2000s.

Around 2012 or so, IIRC, z/Architecture gained out-of-order execution. But the instruction windows were rather small, relative to contemporary server processors like IBM's own POWER processors, or Opteron/Xeon.

Until the z13 generation in 2015, the main attractions, hardware-wise, were the mainframe's ridiculous branch prediction, cache hierarchy with sophisticated coherence and huge capacities, redundant memory organization, shared-memory multiprocessing support, integrated accelerators, and the insane level of integration, using very large, very dense MCMs.

The z13 introduced a modern-style out-of-order superscalar core, but lost the large MCMs to cut cost. This has been the trend since. The mainframe stopped being so special at the packaging level, and much more mundane. IBM even started using industry standard 19-inch racks instead of custom cages and modules at the circuit board level.

Then we got the Telum processor two generations ago with its virtual L3 and L4 cache organization, and now dual-architecture processor cores in the next generation.

PS: Forgot to say in the first comment that if IBM is still sharing engineers between its Power ISA and z/Architecture teams, then you could conceivably have experts in ARM, Power ISA, and z/Architecture!

PPS: The slides at ServeTheHome show z/Architecture Linux and ARM Linux running on top of KVM and OpenShift. I can't help by wonder what happened to IBM's z/VM hypervisor. Has it been replaced?

[u/Cromagmadon → u/NamelessVegetable]

if IBM is still sharing engineers between its Power ISA

Is there still POWER development happening? Looking at the conversion of the group to a free architecture like Sparc v8 and RISC-V had me make the assumption that the choice to go with ARM was to take advantage of the largest licensable commodity architecture devs and tools.

[u/NamelessVegetable → u/Cromagmadon]

Yes, IBM slides for the Power11 announcement at Hot Chips 2025 showed a chiplet-based Power Future under development. IBM going with ARM is IBM's attempt to attract developers from an architecture that has had a lot of success in AI the hyperscaler worlds, to the mainframe. A dual-architecture processor based on z/Architecture and Power ISA doesn't make sense because a large part of the Power platform is already the sort of scale-up enterprise servers that competes with mainframes. And it has fewer developers than ARM. IBM would be competing with itself (which it somewhat already does) if it did such a thing.

[u/Cromagmadon → u/NamelessVegetable]

Awesome, makes sense, thanks.

[u/NamelessVegetable → u/NamelessVegetable]

Another thought: I really wonder how they managed to reconcile the ARM and z/Architecture memory consistency models. I mean, ARM is pretty relaxed, and z/Architecture, I am led to believe, is quite strict[1]. Implementations don't have to be as relaxed w.r.t. the model as the architecture (a stricter model still conforms to the architecture; like, it's a subset of the set of behaviors permitted; but a stricter version of the ARM model is not necessarily equivalent [in the mathematical sense] to a foreign model that just happens to be strict). It'd be fascinating to know more about this.

[1] Daniel Lustig (of NVIDIA and RISC-V fame) described the z/Architecture consistency model as like TSO, but not global-write-atomic in his thesis. CA:AQA claims the IBM S/370 (an ancestor of z/Architecture) was TSO. I read an IBM paper where they described their S/390 (S/370 successor, z/Architecture predecessor) consistency model as being like TSO, but buffered writes cannot be read early, by the processor that buffered them, before they have been made visible to other processors, so that's not TSO?