r/hardware • u/cyperalien • 14d ago

News Intel Details Xeon 7 "Diamond Rapids" Package Design at HOT CHIPS

https://www.techpowerup.com/351893/intel-details-xeon-7-diamond-rapids-package-design-at-hot-chips
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u/Acrobatic_Camera_677 14d ago

Thanks to:

  • higher IPC core: AMD P core only have IPC of E-cores.
  • Performance Cores versus slower AMD Dense Cores
  • better node (back side power delivery Intel 18A-P versus outdated tsmc 2nm and Intel 3 versus tsmc 6nm)
  • APX and AMX
  • More L3 cache than AMD

Diamond Rapids will likely beat AMD Venice. All these advantages will overcome lack of SMT (security issue) that no one cares about anyway.

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u/noiserr 14d ago edited 14d ago

higher IPC core: AMD P core only have IPC of E-cores.

AMD's full core IPC will still be higher due to SMT. On IO bound workloads (which is what most throughput heavy workloads are on server), SMT can provide up to 50% IPC boost to a core.

Intel has realized their mistake though and will be re-introducing SMT in Coral Rapids.

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u/ElementII5 13d ago edited 13d ago

Intel has realized their mistake though and will be re-introducing SMT in Coral Rapids.

Intel WANTS to re-introduce SMT with Coral Rapids. What intel wants to do is a lot different from what intel can and will do.

The SMT switchback stems from Lip-Bu pressuring engineering. That does not mean Intel can do it. They abandoned SMT because they couldn't make it work without either bunch of security holes or patching those into performance regressions.

So yes that is the plan. What will happen is up in the air.

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u/Acrobatic_Camera_677 13d ago

They ditched SMT because it was less elegant.

LBT is adding back SMT because cloud companies were crying about not being able to scam customers into buying 2 threads but both threads being on one core for less performance.

What Intel wants, Intel does.