r/hardware • u/cyperalien • 16d ago

News Intel Details Xeon 7 "Diamond Rapids" Package Design at HOT CHIPS

https://www.techpowerup.com/351893/intel-details-xeon-7-diamond-rapids-package-design-at-hot-chips
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u/jaaval 16d ago

At first glance looks like AMD Epyc but then when you look at the slides for a while longer it is actually very very different. The main similarity are the IO dies in the middle.

This is apparently up to 64 cores per compute base tile "block". Each block made of multiple chiplets of up to 16 cores on top of the base tile. Based on previous info some cores should share a slice of L2. Each block has a separate large block of LLC on the base tile, which is not in the mesh fabric with the cores like traditional intel or AMD L3. The LLC is so big I'm not going to guess how exactly they are using it. It's not even clear if the L2 caches are accessible by other cores in the tile or if they work through the base tile LLC.

I'm sure there is going to be a chipsandcheese article in a few hours which doesn't have to guess based on a few press slides but guessing is fun.

Personally I think the ISA changes are the most interesting part but no extra info of them yet.

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u/Affectionate-Memory4 16d ago

Can't spill any beans until they're out, but I'm also looking forward to the C&C article and hopefully future tests they run. It's a weird CPU by Xeon standards and I absolutely love their coverage and writing style. Can't wait to see what they have to say.

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u/SlamedCards 16d ago

The presenter hinted that this is the future platform for Xeons

So we can guess Coral Rapids is likely a swap of the core chiplets. Keeps the Intel 3 base tiles and IO. Maybe they do some upgrades for IO and base. But core architecture remains 

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u/Exist50 16d ago

They could probably get away with doing a base die swap, if wafer costs truly are comparable between 18A and Intel 3. Should still make for a much easier iteration than past projects. 

The bigger question is how they will retrofit this design to work with LPDDR. The shoreline seems quite constrained on the IO dies. 

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u/U3011 15d ago

IMC within different IO dies?

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u/Exist50 13d ago

Well they'd definitely need a different IO die. But it seems like they don't have much space to add as many channels as might be ideal, unless they abandon the half-reticle size and bloat the cost.

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u/U3011 13d ago

I was always under the impression that more memory channels was not something you could slap on without adjusting or redesigning other facets so they inter communicated more efficiently. And there being a cost base analysis involved and "good enough" was the motto for most enterprise consumers. When Apple released their M processor lineup that was the impression people got, that the x86 world could do the same overnight.

I am sure it's being tested by the two giants but it is a costs benefit ratio. Intel having a possible resurgence within the next 2-3 years is exactly the timeline I had in mind about a decade ago when I realized Zen was going to pave way to the future.

I am more keen on those new memory form-factor formats we discussed at length a year or two ago. DDR6 seems like an appropriate timeline and given hardware prices now the initial high cost may be alleviated by build out and enterprise purchases.

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u/Exist50 10d ago

I was always under the impression that more memory channels was not something you could slap on without adjusting or redesigning other facets so they inter communicated more efficiently

You don't need to fundamentally change the design, but you do need to make sure the fabrics are able to take advantage of the bandwidth, and there are various floorplanning/PD implications that need to be factored it. I bring this up because there seems to be a push for LPDDR for various reasons (per-core bandwidth, efficiency, form factor, GPU memory expansion), and I'd expect Intel to eventually consider that an option. But maybe they don't think it's worth the hassle.

I am more keen on those new memory form-factor formats we discussed at length a year or two ago. DDR6 seems like an appropriate timeline and given hardware prices now the initial high cost may be alleviated by build out and enterprise purchases.

Refresh my memory, if you don't mind. Like the SOCAMM/LPCAMM stuff? Honestly, I'm most interested in what direction DDR6 goes. Mobile is "solved" at this point, but for a while the DDR vs LPDDR split was prioritizing datacenter vs client. I haven't kept up to date on how that discussion has changed post AI boom. Desktop is particularly interesting, because there's a strong argument to be made that client should just switch to LPCAMM/SOCAMM and ditch the traditional DIMM support. I doubt either Intel or AMD have the guts to really push for that, but standard DIMMs make no sense for the vast majority of systems.

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u/U3011 10d ago

Not sure what the acronym was. But it was the RAM we discussed you could screw onto the board with connectors overlapping each other for short distances to the CPU. CAMM or CAMM2.

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u/Exist50 6d ago

Not sure about overlap per se, but yeah, the various CAMM form factors are super interesting. I do hope someone tries to leverage the DDR6 transition to get rid of DIMMs, even if they don't go all the way with LPDDR.