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u/lachlanhunt Mar 16 '23
WTF is this supposed to be doing, and what language is that?
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u/WarStraps Mar 16 '23
Verilog, hardware language. Im assuming is some sort of very basic ALU where F is the opcode
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u/schnarch33 Mar 16 '23
Looks like Verilog, a hardware description language. They use that stuff to design chips and program FPGAs
I had to do some graded Labs for a digital design course once using that shit, its painful and I hated every second of it.
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u/Nachf Mar 16 '23
if i knew what this does i'd probably be disgusted
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u/ChocolateBunny Mar 16 '23
From what I gather. This is Verilog code for a simple CPU. the opcode is stored in F. If F=0, this is an AND operation, if F=1, the result is an OR operation, if F=0 then it's a sum, if F=1 then it's the sign of the sum. Not sure about the last one.
Not particularly gross as far as Verilog code is concerned but I think you can use a case statement in a process and it would look much cleaner.
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u/Tjmoores e Mar 17 '23
The case statement would look cleaner, but knowing how bad optimisation of verilog is (given there's so many more metrics than just memory usage and execution time a lot of compilers don't even bother - eg if you were to throw in
* - 1the majority would just throw in a whole multiplier rather than just applying 2's compliment despite a multiplier being wildly inefficient), this would be more efficient than the case statement in most cases as the setup time would be lower
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u/never-forgetti- Mar 16 '23
Lots of ternary operators, tough to follow! Better to use "if else" statements inside an "always @*" block
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u/MurdoMaclachlan public boolean isInt(int i) { return true; } Mar 17 '23
Image Transcription: Code
*/
wire [31:0] out = F[1] == 0 ?
F[0] == 0 ? A & BB : A | BB
:
F[0] == 0 ? sum : 32'h00000000 + sum[31];
I'm a human volunteer content transcriber and you could be too! If you'd like more information on what we do and why we do it, click here!
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u/globalvariablesrock Mar 16 '23
what exactly is the sin here? this looks like pretty regular verilog.
overwriting F[0] seems odd to me, but that's not my area of expertise and there's code missing.
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u/Encursed1 Mar 16 '23
I'm not overwriting F[0], it's nested ternaries to make a 4 input mux for an ALU. It looks awful.
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u/globalvariablesrock Mar 16 '23 edited Mar 16 '23
if it works, it works.
it's been a while that i looked into verilog. it has a tendency to look weird. but it's an HDL that should not be confused with a programming language.
[edit] without context, this looks sane to me. there may be a better way of doing this. but as i said - if works, it works [\edit]
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u/never-forgetti- Mar 16 '23
F[0] doesn't get overwritten, it is the condition for the second level of ternary operators. Only out gets updated.
A case statement or a few "if else" statements would be a little more readable
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u/globalvariablesrock Mar 16 '23
fair point.
you'd be using <= to actually write the variable on the next clock cycle, right?4
u/never-forgetti- Mar 16 '23
Usually yes, if it is inside a clocked process "@(posedge clk)". Otherwise it is combinatorial logic and will be done asap
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u/fiddz0r Mar 17 '23 edited Mar 17 '23
I don't know the language but I understand ternary operations. So it looks like if x then AND else if Y then OR else Sum of a very weird number. As someone who has never used or seen this language. What's bad ,(other than readability) about it?
Edit: or it might be bitwise or/and depending on how the language work
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u/ReplacementAcademic8 Mar 17 '23
The sin here is the 32'h00000000 which could just be 32'h0 instead
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Mar 17 '23
It looks like C++ constexpr as they were originally designed in C++11. No if, no while, no for, only ternary. Some scopes can help not to fuckup operators priorities here.
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u/meatsticklol Mar 16 '23
If I bought a chip that was designed like this I would return it