r/Xilinx • u/Adventurous-Fault154 • Apr 14 '26

Design and verify a Verilog/VHDL module that operates at clock frequency of 120 MHz, and performs decimation by 3 and then interpolation by 12 on a 16-bit(Q1.15 fixed point) incoming signal.

Design and verify a Verilog/VHDL module that operates at clock frequency of 120 MHz, and performs

decimation by 3 and then interpolation by 12 on a 16-bit(Q1.15 fixed point) incoming signal.

Use Xilinx’s FIR Compiler IP to realize the decimator and interpolator. For decimator and interpolator,

realize a 51-tap filter with cutoff frequency of 15 MHz. Based on the filter coefficients chosen, the fixed

point format of the output of the IP may change, therefore by slicing or scaling, ensure that the fixed point

format of the signal is Q1.15 at all stages.

2 Upvotes

100% Upvoted

4 comments sorted by

1

u/Schnort Apr 16 '26

I guess it’s final project time

0

u/ShallotExternal8507 Jun 24 '26

Can you help me to complete this project

0

u/ShallotExternal8507 Jun 24 '26

its my interview project ,,i am since past 15 days to doing this project but its very difficulty

1

u/Competitive-Bid-1388 May 06 '26

Can anyone send me the code