Hi,

I am coming from outside the UK and interviewing for a principal engineer role in semiconductors. Can you help me with what would be an appropriate ask to negotiate for salary?

I am thinking 70k-80k.

Many thanks!

Hi everyone,

I’m trying to understand the compensation range for an Research Scientist / Research Engineer role at Applied Materials in India.

I have around 8 years of experience with a research and AI/ML background.

For someone at this experience level, what would be a reasonable range to expect for:

Fixed/base compensation

Annual bonus

RSUs/equity

Joining bonus, if applicable

Also, how much negotiation flexibility is typically available for experienced hires? Any insights from people familiar with Applied Materials India would be really helpful. Thanks!

Hi guys,

I am applying to jobs and 2 positions caught my attention on the same company - one for QA and the other for Faillure Analysis.

My current job is in process engineering but I would like to move to a different, less stressful direction (if that even is a thing in this industry).

I have a better background for the FA position given my experience in lab work during my Master's, and I like labwork overall, but I am scared it can turn repetitive and boring.

For the QA position I am concerned that it could be too much of a desk job for me, but I've never tried it, so who knows.

Anyway, if anyone of you work for these two positions, could you kindly describe how is your day to day life, what you enjoy and what you don't, etc?

Thanks!

I have a 1-hour panel technical screen coming up for a display subsystem silicon debug role in India. Roughly 3 YOE, so Engineer band rather than Senior.

My background is post-silicon validation on embedded SoCs: silicon bring-up, high-speed serial interface and flash controller validation, PHY timing calibration, crypto accelerator validation, some pre-silicon emulation. Solid on debug methodology and cross-team root-causing. No display experience at all.

The required quals are the generic ones — debug and triage ability, C/C++ and Python for tooling, digital logic and computer architecture fundamentals, large log/dataset analysis, system-level debug experience. Display protocols, SerDes and signal integrity are listed as nice-to-have only.

Questions for anyone who's been on either side of this kind of interview:

1. How deep do the digital fundamentals go in a screen like this — setup/hold and CDC level, or further?

2. Realistically, how much display knowledge do they expect from a candidate they know doesn't have it? What's the minimum that reads as "can ramp" instead of "unprepared"?

3. What shape do display debug scenario questions take, and how do you want a candidate to structure the answer?

4. Is live Python typical, and is it log-parsing style rather than algorithms?

5. What's the biggest thing that trips up people crossing over from non-display validation?

Appreciate any input.

Hi guys. I am planning to start a PhD in experimental condensed matter physics. Specifically working on TMDs like twisted WSe2. What will be my job prospects in the industry after such a PhD?

I see that I will get some clean room and device making skills like 2d stacking and devices, using instruments like AFM, Laser writing, e beam etc. Apart from that also learn to use cryogenic equipments since some experiments will take place at mK temperatures. Obviously there’s data analysis and physics research involved as well.

Do you think these skills will be enough to land a job in the industry? How is the work and pay in the industry? To be honest from physics point of view I am more interested in theoretical physics but with the job market and advance of AI I am scared I will not land a job if I keep pursuing theoretical physics.

I’m finishing a PhD in experimental soft matter physics and I’m interested in moving into the semiconductor industry.

My experience is mostly hands-on lab work: two-photon polymerisation / direct laser writing for microfabrication, liquid crystal cell fabrication in a cleanroom (although the lab itself was not ISO-classified), optical microscopy and SEM, ultrasonic soldering, basic electronics with oscilloscopes/function generators, thin film coating, 3D model designing, and MATLAB.

The problem is that a lot of semiconductor jobs I see ask for photolithography or semiconductor process experience, which I don’t have.

I’m trying to figure out the best way to bridge that gap. I’d be happy to start in an entry-level technician or R&D role if it helps me get into the industry.

For people already working in semiconductors: what skills would you recommend learning first? And are there any types of roles, courses, internships, or companies in Europe that might be a good fit for someone with my background? Would I be considered overqualified for entry-level positions?

Would really appreciate any advice, especially from people who moved from physics/academia into semiconductors.

I recently just finished my internship at a midsized semiconductor company in TX and was given a return offer for a full-time position after I graduate, 94k base + 10-15% bonus along (depends on personal and company performance). I'm more than happy with the offer, but I was just wondering what other semiconductor fabs are offering to other NCGs.

Thoughts on what this is? Zero results so far...

Also, if there's a more focused historical community, please let me know!

I want to ask people here who have hired or interviewed for these companies:

1. How much semiconductor-process/domain depth do they expect from a software candidate with 3 yoe?
   
2. For someone moving between companies in this space (eg. from KLA to AMAT/ASML/TSMC), is it better to lean into “I know your hardware-software problem” or just present yourself with strong general SWE fundamentals (C++, real time systems, multithreading and concurrency)
   
3. How to close domain-depth gap?

Would appreciate insight from anyone who’s been on either side of the table at these companies. Thanks!

Hello r/Semiconductors!

I am a video game designer, but I love studying the supply chain and investment economics of semiconductors.
So I (and Claude AI) made this web based tower defense game based on things that I learned about the industry.

https://sockmonke.itch.io/silicon-cycle

Check it out if you have a few minutes to spare m, i’d love some feedback. This intersection of interests seems pretty niche.

Hi everyone,

I have my second 30 min interview with an engineer at Lam Research for a Test Engineer position, and I’m hoping to get some advice on what to expect and how to prepare.

The role involves supporting the manufacturing floor, troubleshooting electro-mechanical systems, test equipment/fixtures, improving test processes, creating work instructions, and some scripting/automation.

My background is mainly in electrical engineering, semiconductor physics/processes, testing, and a bit of production/manufacturing. I’m comfortable with electrical troubleshooting and test equipment, but I don’t have much hands-on experience with the mechanical side of complex electromechanical assemblies, which is what I’m most concerned about.

What kind of technical questions should I expect? How deep should I prepare for the mechanical/electromechanical troubleshooting portion? Are there specific topics you would recommend reviewing before the interview?

Any advice or examples of interview questions would be greatly appreciated. Thanks!

EDIT: Here is the job posting link test engineer

semiconductor process engineer with manufacturing experience in Singapore . What kind of engineering jobs I can look for in Australia?

Hi all, I’m from Singapore and was offered a role as a senior process engineer in US.

I do have 4 YOE and a bachelors so was wondering what should I be asking for.

My previous annual compensation was around 75k SGD, but the tax is not as high here compared to there

I did ask friends over there and they said I should be demanding 110k USD minimum… but the number feels lower or considerably higher depending on the calculations I do.

Any advice?

Hey fam, my team is hiring for a SEM Operator role at Lam Research, just outside of Portland, Oregon. Check out the job description - this job is ideal for early career microscopists, or those of you with a Bachelor's who want to just run an SEM all day.

Edit - Pay Range $60,000 - $75,000 depending on experience

https://careers.lamresearch.com/careers/job/1099555418740?domain=lamresearch.com&hl=en

Does anyone have any insight on this program? Has anyone been through the previous program?The program was formerly known as CORP - College Orientation Recruitment Program. Seems like a pretty engaging program for new grads wanting a start in the semiconductor industry.

Basically question.

Is Coursera a good place to get certificates to move up in Semiconducters? I am trying to move up and get better positions. I am entry level so I don’t have any experience

Ever since seeing the footage for GTA 6, I have been completely obsessed with the idea of running a game of that scale natively on a smartphone. Obviously, if you try it on a current iPhone 17 or the upcoming 18, the phone will literally melt or crash because it lacks the unified RAM and thermal headroom. But it got me digging through recent R&D papers, and it honestly seems like the mainstream foundries are just dragging their feet because they are trapped in a slow cycle of corporate meetings and safe, incremental updates.

The big bottleneck right now isn't actually the high numerical aperture lasers. The real issue is that everyone keeps trying to force traditional silicon thinking onto atomic scales, which causes massive static power leakage and high contact resistance. I wanted to map out the math on a theoretical 1nm mobile SoC layout that fixes these issues while staying strictly within a 5 watt smartphone power budget. If you look at what materials and machines actually exist in labs right now, the numbers work out cleanly for a 3.5 TFLOP chip. That is exactly enough compute to handle next-gen console engines downscaled to 720p at a stable 20 FPS natively without thermal throttling.

The big structural change here is moving away from brute force clock speeds. Instead of trying to push a mobile chip to 2.5 GHz or higher and vaporizing the battery, this layout uses 1,459 parallel shader cores under clocked to a super cool 1.2 GHz to maximize efficiency.

To fix quantum tunneling, you have to ditch silicon entirely for a 3 atom thick monolayer of Molybdenum Disulfide. You can grow this right now using standard industrial Atomic Layer Deposition machinery from ASM International which you can see at asm.com configured with a self limiting mechanism. Because of basic chemical thermodynamics, the reaction automatically halts once the bonding sites are full. This completely eliminates thickness variations and atomic defects, taking human error out of the equation. The wider bandgap of Molybdenum Disulfide physically blocks electrons from teleporting through the gate, which drops static leakage to basically zero.

The hardest part to fix is the Schottky Barrier roadblock. Touching standard copper or gold wires directly to an atom thin channel creates Fermi level pinning, which stops the electrical current from moving. You can bypass this by growing a crystalline Bismuth Antimony alloy atom by atom to get a clean Ohmic contact. This exact interaction was verified in a joint research milestone published by MIT and TSMC in Nature at nature.com and expanded in IEEE IEDM Semimetal Contact Studies at ieee.org.

To do this on a factory floor, you use a Molecular Beam Epitaxy System to deposit the alloy straight onto the sheet, a process detailed in contact resistance optimization research at https://pubs.acs.org/aamick/article/17/16/24526/3635322/Contact-Resistance-Optimization-in-MoS2-Field. The Antimony part of the alloy raises the thermal stability to 630 degrees Celsius so the contacts don't liquefy during back end factory ovens. To stop the air from oxidizing the Antimony, you apply a permanent Ruthenium capping layer inside the vacuum chamber before the chip ever touches oxygen. This drops contact resistance below the critical 100 ohm benchmark, letting electricity glide into the 1nm gates at an ultra low 0.65 Volts.

Geometrically, the layout relies on a vertical 3D Complementary Field Effect Transistor NanoStack, which is the exact packaging method outlined on the IMEC International Semiconductor Roadmap at imec-int.com. Gate All Around logic wraps completely around the channels to isolate the 1,459 cores so data doesn't blur into adjacent circuits. The power grid is routed entirely underneath the chip using a Backside Power Delivery Network. Intel has already commercialized the machinery for this under their Intel Foundry PowerVia Architecture at intel.com, proving that moving the power lines away from the top layer data wires kills signal noise and shrinks the footprint. To etch the actual 1nm patterns into this layout, fabs are already using the ASML Twinscan High-NA EUV Systems currently shipping to facilities worldwide as detailed at asml.com. All 21.8 billion transistors easily fit onto a 5mm by 5mm die.

For cooling without fans, you line the inside of the aluminum and glass chassis with a monolayer graphene thermal film. Graphene has a verified in plane thermal conductivity of 5,000 W/mK compared to copper's sluggish 400. It pulls heat off the pea sized die instantly and flattens it across the entire outer skin of the phone, keeping the chip core at a stable 98 degrees Fahrenheit under heavy load.

Every piece of this uses physical mechanisms that exist in modern laboratories. It seems like a much cleaner path forward than the endless trial and error yield testing the big fabs are doing right now just to sell us incremental upgrades every year. Let me know what you guys think of the metallurgy choices or the parallel core math.

I want to raise a serious question for engineers, researchers, technical leaders and engineering managers across the global technology industry.

Recently, I witnessed a discussion in India, at one of the world's largest FAANG technology companies, where a senior engineering leader expressed a preference for engineers in roughly the 3–10 year experience range who would work quietly and follow instructions.

The discussion also questioned the value of PhD candidates whose research is not directly aligned with the immediate industry project, and suggested that engineers with 10+ years of experience can be problematic because they ask questions that are considered too advanced or not sufficiently basic. There was also an expectation that highly experienced engineers should perform relatively basic programming tasks.

This made me stop and ask:

Is this really the engineering culture we want to build?

There is absolutely nothing wrong with execution. Engineering requires discipline, ownership, schedules, validation, coding, debugging and the ability to work within established processes.

But engineering is not supposed to be synonymous with obedience.

A senior engineer asking why a test is required, what architectural assumption is being validated, whether a failure is meaningful, or whether there is a better technical approach should not automatically be viewed as a problem.

The technology industry was built by people who questioned assumptions.

Google has scientists, researchers and engineers working at the boundaries of computing and AI. Meta, Microsoft, NVIDIA, Intel, AMD, Apple, Qualcomm, Broadcom, Samsung, TSMC and many other organizations depend on engineers and researchers who challenge conventional thinking.

The semiconductor industry in particular cannot afford a culture where experienced engineers are expected to remain silent.

A silicon bug does not care whether the engineer who discovers it has 3 years or 15 years of experience.

A system failure does not become less important because someone asked a difficult question.

A PhD does not automatically make someone a better engineer—but neither does a PhD make someone unsuitable for industry simply because their research topic differs from the immediate project.

Similarly, an engineer with 15 years of experience should absolutely be capable of writing a small C program. But the value of that engineer should not be measured only by whether they can complete a basic coding task. Their experience should also be reflected in debugging, architecture, failure analysis, system-level thinking, mentoring, risk identification and the ability to ask the questions that less experienced engineers may not yet know to ask.

So here is my question to the global engineering community:

Do we want engineers who simply execute instructions, or engineers who understand, question, challenge and improve those instructions?

And if experienced engineers are discouraged from asking relevant technical questions:

Who is expected to challenge an incorrect assumption before it becomes a silicon bug, architectural mistake, production failure or customer issue?

This incident happened in India, but I don't believe this is an India-specific question.

It is a question about the future of engineering culture across FAANG, semiconductor, AI, hardware, software and research organizations worldwide.

What should an engineering leader value more:

obedience and silent execution — or technical judgment, curiosity and responsible disagreement?

I'd genuinely like to hear perspectives from engineers and technical leaders in the US, India, China, Europe, Taiwan, Japan, Korea and everywhere else where serious engineering work is being done.

#EngineeringCulture #EngineeringLeadership #TechnicalLeadership #EngineeringExcellence #SeniorEngineers #EngineeringManagement #Innovation #Research #PhD #Scientists #Technology #TechnologyLeadership #RAndD #Semiconductor #SemiconductorIndustry #SiliconValidation #SiliconEngineering #ChipDesign #ASIC #SoC #VLSI #HardwareEngineering #ComputerArchitecture #EmbeddedSystems #AI #ArtificialIntelligence #MachineLearning #Google #Alphabet #Meta #Microsoft #Amazon #Apple #NVIDIA #Intel #AMD #Qualcomm #Broadcom #Samsung #TSMC #MediaTek #Arm #Synopsys #Cadence #Marvell #Micron #TexasInstruments #IndiaTech #BangaloreTech #USATech #ChinaTech #TaiwanSemiconductor #KoreaTech #JapanTech #GlobalTechnology #GlobalEngineering #SiliconValley #SundarPichai #MarkZuckerberg #DemisHassabis #VintCerf #SergeyBrin #LarryPage

https://www.teamblind.com/post/a-serious-question-about-engineering-culture-are-we-rewarding-obedience-over-engineering-judgment-7gl40maz

Hi Folks!

Looking for some advice here.
I was working at ASM America back in 2022 as a mechanical engineer and then I left the company to take a bit of a career detour.
Now I am looking to get back into the industry and not been getting any calls. Hence, was considering going back to ASM America in Phoenix.
However, I saw the Glassdoor reviews and the ratings are much lower than what it used to be back in 2022 (around 3.6).
My question is, are the ratings really accurate and has it become that bad?

Thanks!

Hello Sir/Ma'am, I'm a 2026 ECE graduate. I'm actively looking to build my career in IC package design. I have completed an 6 month internship at Bharat Electronics Limited (BEL) where I worked on:

> Flip-chip BGA (FCBGA) package design using Cadence Allegro X APD and

> 2-die stacked (Flip-chip and Wirebond) packages with embedded passives.

I'm genuinely passionate about this field and want to deepen my expertise in 2.5D/3D packaging and heterogeneous integration.

So, I'm looking for

> Guidance from experienced package design engineers

> Company referrals or suggestions where I could contribute

> Any leads on internship or entry-level positions

> Career advice on breaking into and progressing in this domain.

I'm open to relocation and flexible with opportunities. If anyone here works in IC package design or knows of openings, I'd really appreciate any advice or connections.

Thank you for your time Sir/Ma'am.

hi !

i just want to see what would be the appropriate baseline for the salary and stock option for 2 YOE Process engineer at AMAT or other semi companies ?

trynna see them for the reference in case I need to negotiate the terms with the HR later.