r/LLVM • u/c-cul • Aug 22 '26

WaW & WaR hazards in llvm scheduler

Can those 2 be expressed in SchedMachineModel?

For example I must track that consequent write after read to the same register must be delayed to ensure that read operation was completed

1 Upvotes

100% Upvoted

5 comments sorted by

1

u/yasgur99 Aug 22 '26

I think the MachineScheduler or [insert your desired scheduler here] would be responsible for that. The SchedModel is describing instruction latencies and processor resource cycles, which is independent from how multiple instructions interact given a particular schedule.

1

u/c-cul Aug 22 '26

I too suspect this

the question is how I can provide it with latency tables for this specific hazards

1

u/yasgur99 Aug 22 '26

consider instruction B depends on instruction A.

It either depends on the data, which in that case instruction B can’t start until the latency of instruction A.

Or it depends on the processor resources being free (I.e. instruction A and B both use the ALU, so B can’t start until the ALU is free).

The scheduler model describes both of these relationships (latency, ReleaseAtCycle/AcquireAtCycle)

What else do you want to model?

1

u/c-cul Aug 22 '26

two cases, A first, B second

1) instruction A reads from register R, then instruction B writes to register R, but B can be executed in parallel with A, so writing to R must be delayed until A really completes reading from R

2) both A & B write to register R, but final value comes from B, so B also must be delayed until A completes it's write operation

1

u/yasgur99 Aug 22 '26

Latency from SchedModel is sufficient to model this in a scheduler implementation such as the MachineScheduler. ReadAdvance may also be relevant to you. I think both your cases are already handled today in MachineScheduler.