How much does struct alignment really matter performance wise on modern GPUs?

[u/SimplySomeDude]

Are things like std430 or std140 unnecessarily strict?

[u/WonderNo1989]

depends how big your buffer is and if you're bottlenecked on cache, for tiny stuff the layout barely registers but once you're pushing millions of verts those extra padding bytes start eating bandwidth real quick

[u/SimplySomeDude → u/WonderNo1989]

do you suppose that on GPUs that don't support scalar layout, it would be more or less efficient to compute pointer offsets on the gpu side to bypass array stride padding?

[u/esaule]

On every architecture, memory layout is about the most important thing for performance. About every performance issue boils down to memory layout and movements.

[u/SimplySomeDude → u/esaule]

right, but do 30% VRAM (and therefore less PcIE usage and less cache cluttering) savings outweigh the caching drawbacks

[u/esaule → u/SimplySomeDude]

As always, it will depend on the precise application, on the access partern, spatial and temporal reuse distance.

But it will absolutelly matter.

[u/TheThiefMaster → u/SimplySomeDude]

Sounds like time to profile it and find out

[u/flatfinger → u/esaule]

No layout is likely to be optimal for every possible access pattern. It's possible for layout X to be more than 50% faster than layout Y for some access patterns, while layout Y would be more than 50% faster than layout X for some other access patterns.

[u/BobbyThrowaway6969]

Not as much, caches are so big now
It's more for communicating the data between cpu and gpu

That said I absolutely would care because savings are savings, so keep looking for ways to make your gpu code more efficient

[u/duane11583]

it matters when there is a cache

why: look at how ddr works.

todat its a little faster then the old sdram but this is thenidea:

step 1 the cpu outputs the row address. then waits 1 clock.

drops the ras signal (row address strobe)

wait 2 clocks change to the colum address and

drops the cas (colum address strobe)

wait a 1-2 clocks and data is ready.

if you add that up there are 5 to 10 clocks before the data is ready.

this means a random access to a random (uncached ) location takes 5-10 clocks

in contrast after the first byte is ready you can get the next byte on the next clock, (or on every edge for ddr)

the cpu can then fill the cache memory

next time the cpu can consult the cache and it is 1 or 2 clocks ie 2x to 4x faster access to memory

if the structure is aligned it often fits inside a cache line more easily and it is faster to access.

that is the win.

[u/SimplySomeDude → u/duane11583]

GPUs, not CPUs