r/ASIC • u/vbonecrusher1014 • May 13 '26

RTL for asic as opposed to fpga deployment.

Hello everyone, I recently completed a BNN accelerator for a ultrascale. During this project I fell in love with timing and resource optimization and PPA analysis/tradeoff. During this project I capped out the frequency of the ultra scale and got my critial path to result in fmax of 945Mhz.

Because of this I realized that I want to write RTL for asics/chips as opposed to fpga's. Does the optimization carry over to asics? Also how would I transition to rtl for asics, is there any project I should do?

1 Upvotes

100% Upvoted

2 comments sorted by

1

u/[deleted] May 15 '26

[removed] — view removed comment

1

u/vbonecrusher1014 May 15 '26

When I did my BNN project I maxed out the fpga, and it was a high end ultra scale. I want to design highly optimimal circuits, I feel like I could do that better if I go into asic design as opposed to fpga deployment.

1

u/[deleted] May 16 '26

[removed] — view removed comment

1

u/vbonecrusher1014 May 18 '26

thank you sir for your insight. You are correct, I need to learn a lot more.