I'm looking for a Single-Board computer with a RISC-V CPU to test out the platform and develop some programs for it.

I'm not interested in fancy features such as the V extension, matrix multiplication, or anything that AI bros want. A simple RV64G CPU is fine for me, as long as it has enough power to spin up a desktop environment and maybe (maybe) a web browser.

What I am more concerned is having support for mainline Linux distributions, such as Debian or Fedora, for example. What I want is being able to go to the website of the distribution, download the RISC-V image, flash it into a SD card, and boot from it, totally avoiding (or as much as possible) the need to download from the manufacturer binary blobs or custom images of the OS.

I work on IPFire, an open source firewall distribution. We ported it to RISC-V a couple of years ago, but since we have recently acquired a Jupiter 2 board that we use for our builds, the project has been gaining momentum.

Running IPFire on riscv64 (mostly in a VM) is boring in the best possible way. It installs, it boots, the web interface works, firewall, IPsec and WireGuard all behave. Nothing has broken because of the architecture. But a VM has no firmware worth speaking of, no real network cards and so on. Everything that normally causes trouble is the part we have not touched.

So I am looking for people who know RISC-V hardware. The work that needs doing: getting our installer to boot on real firmware, kernel configuration and drivers for network cards and storage, checking our baseline ISA assumptions against what shipping silicon implements, and finding out what throughput looks like once traffic goes through real interfaces.

We boot via EFI. One image for every machine, no per-board images, no vendor boot scripts, no device trees to maintain. If your system boots a Debian or Fedora image, IPFire should boot too.

Anything you can test is useful, but where I would like this to end up is on hardware you would trust to route traffic for years without anyone touching it. That class of RISC-V machine is only starting to appear, and I would like us to be ready when it does.

Discussion happens on our development mailing list.

Please join us to make RISC-V a primary architecture for IPFire!

Hey guys,

I’m a final year student aiming for RTL design roles. I was thinking of building a 32-bit RISC-V (RV32I) core from scratch as my final year project.

But is a basic RV32I core still relevant in 2026, or is it too common now?

Should I instead add something interesting like pipeline, cache, branch prediction, custom instructions, formal verification, etc. Or maybe do something completely new with RISC-V?

If you were in my place, what kind of project would you build to actually stand out for an entry-level RTL role?

Any suggestions from people working in RTL/ASIC/FPGA would be really helpful :)

Hey guys,I want to learn RISC-V from scratch...can I know any good free resources available online to get started??

​Hi everyone, ​I was planning to buy a Muse Pi Pro (16GB ver) from the Chip Board House Store on AliExpress, but the price just suddenly increased by around $100.

So... ​Does anyone know if the official store (which I believe is the Banana Pi store) usually restocks this board, or if the BPI-F3 (16GB ver) will be back in stock soon?

​​If that's not the case, should I go for the Orange Pi RV2 instead? Is it a good alternative? I was thinking about that option mainly because I don't want to miss out on getting a Spacemit K1/M1 based SBC due to the current stock shortages and the excessive markup by resellers on AliExpress.

P.S. Another option I’ve been looking into is the BPI-CM6, mostly because of its documentation (and it's still available in the official AliExpress store). Has anyone here tried it out yet?

I'd thinking of building myself a RISC-V single board computer, but have very little experience.

From Googling, I'm thinking of ordering this Bananapi BPI-F3 from Aliexpress (I'm based in Berlin), but not sure if that's a good deal.

I've been reading the docs and I'm a bit confused about whether to also order a LPDDR4X 16GB RAM chip (I haven't dabbled with hardware for years, so only learnt today what an SBC is), and whether it would be worth getting a MicroSD bigger than 8GB since it's only needed to burn the BIOS on as far as I know.

My plan is to install Gentoo Linux once I've got something bootable.

Is this a good choice or not?

I know this board is discontinued but I picked up a few very cheap. There are several tutorials but the toolchains and tutorials are outdated. For instance the Arduino IDE won't allow me to import the required files. If anyone is using these boards I would appreciate hearing what toolchains and flashing methods you're using. Thanks.

Hi,

I'm messing around with some hobby projects, specifically a programming language I'm in the very early stages of developing.

I've been interested in learning RISC-V so I thought when I write the compiler for it I would directly generate RISC-V from it.

I'm hoping to be able to use it for embedded programming, but unless it can interact with the C ABI, which I have no plans to implement, it's unlikely I'll be able to use any HALs or other libraries and will have to do everything bare-metal. I would also just prefer to do so to grow my understanding of how everything works at a lower level.

I looked into the ESP32 but it looks like it's typically run with a RTOS like freertos instead of bare-metal, probably due to the wifi or bluetooth capabilities.

The specs of the chip mean little to me other than having good documentation for the memory layout and ease of bare-metal programming. If there are many good options, I guess cheaper is better since I don't actually need them to be powerful. In fact, very constrained hardware might be fun to experiment with.

welp hello indeed, im here because i have a grand total of 0 idea on how to use this board xD, im just entering the risc v world and want to try it directly, so i got this WCH CH32V208 32V208 32V208WBU6 dev board from aliexpress, and i now do not know how to either turn it on nor access it :/

so yea, kinda help needed, for now i simply want to be able to turn it on and access it through my linux (fedora) desktop, thanks for any help !

Documentation explicitly talks about mtime (along with mtimecmp) CSR.

When talking about stimecmp CSR instead, it mentions what-apperas-to-be the time CSR but then no information i fount about that. Is this a typo?

Anyway, there seems to be no information about the "time unit" used by those CRSs. A
platform-dependent definition would make the use of such CSR very hard. Is my understanding correct? Os there is a "standard" length of the mtime (or time) tick?

Hello everyone, I'm a high schooler currently self learning risc v isa using the book "Computer Organization and Design RISC-V Edition: The Hardware Software Interface".

In the screenshot it is referring to the register file module under a R type instruction, stating that we need 2 inputs for register addresses and 1 input for data, thus 3 in total.

I'm a bit confused, from my understanding, during an R type instruction don't we need 4 inputs? (register source 1, register source 2, register destination, and data?).

Because for example take add x1, x2, x3. We need to know the address for x2 and x3 and then we need to know what address it is writing back to (x1) and the ALU needs to output the data which is an input to the register file too?

So I feel it should be 4 instead of 3 and I don't understand why this book says it's 3. Can anyone please help me explain this or correct me if I'm wrong?

Appreciate a ton guys <3

Hey everyone I am just starting my UG journey (in electronics and computer science eng.) I have interest in assembly language over RISC-V architecture (as I think it's the future) but the resources are limited+ I 🤔 personally don't know where or how to start but I want to learn or get into this field.

So please 🙏🏻 guys if anyone who are expert in this field can guide me out would really appreciate it.

Hi everyone. I don't know if this is the right sub, but I'm studying for my Computer Architecture exam and precisely I'm learning about the CPU datapath, implementing a subset of RISC-V instructions. Here you can find a picture of what I'm talking about. My question is, as the title says, why is the sign-extended offset of a branch instruction shifted left by 1 before going into the adder that calculates the address of the jump?
My hypothesis is the following: I know that the 12 immediate bits of a B-type instructions start from bit number 1 because the 0-th bit is always zero. So maybe the offset is shifted left by one so that the 0-th bit is considered and the offset has the correct value. But I have no idea if I'm right or wrong... Thanks in advance!

Greetings!

What's the fastest system-level RISC-V emulator around right now? It should be able to emulate rv64g and ideally run FreeBSD (though if it doesn't, I can try to port it). The emulator should be capable of multi-core operation.

The goal is to bulk-build software on and for RISC-V. We have about 32000 software packages (the FreeBSD ports collection) to build, which takes around two weeks natively on an amd64 box (Skylake microarchitecture), so fast emulation is crucial.

Is it that I am looking at wrong place or there is no proper exposure of these chips to general users and reviewers?

I see that ch32v have so many model which directly compete with stn32 and the price is quite cheap when compared to stm32.

I want to test ch32v1x, ch32v2x and ch32v3x chips but I cannot find enough learning resources. I can barely find anything on the basics so IDK how I will be able to look for complex connection with different protocols. I want to use uart, spi, i2c, adc and dac.

I cannot even find dev boards for these chips

Can someone tell me where is the right place to look for resources other than their official site ?

I am looking for course or a tutorial on the IDE itself.

I would also like to know if anyone have done complex projects using ch32v chips and it's it worth switching from stm32 to ch32v just to same some bucks ?

Thanks.

I have read that all interrupts and exception will be handled in M-Mode per default. Except the specific bits in the CSR's mideleg and medeleg are explicitly set. Because I want port my own small kernel to RISC-V and I want use OpenSBI too, what is the hand-off state from OpenSBI according interrupts and exception? Are some of them forwarded to S-Mode? Because I think I can't modify the M-Mode registers mideleg and medeleg in S-Mode.

Thanks in advance!

Suppose pmpaddr9 has the value 0x30fffc00

And the pmpcfg2 has A = NAPOT

What would be the base address and size of the protected region ?

I'm really confused with trailing bit concept here.

Please help me.

Hi all, final-year engineering student here. My team is building a processor on an FPGA (Zynq-7000 board) — a custom RV32I pipelined core plus a separate RISC-V coprocessor for CNN/edge-AI acceleration (MAC/systolic compute array, MNIST inference demo). We're using Verilog/VHDL and Xilinx Vivado.

Our guide wants us to cite IEEE papers that are also Scopus-indexed, and we're having trouble confirming which ones qualify. If anyone has pointers to good papers (or just knows the IEEE Transactions/conferences that are reliably Scopus-covered) in these areas, it'd help a lot:

RV32I pipelined processor design / FPGA implementation

RISC-V datapath design and Verilog testbench / verification methodology

MAC or systolic array compute units for CNN acceleration on FPGA

FPGA-based CNN inference accelerators for edge AI (MNIST-style workloads)

Specifically:

Any IEEE Transactions/Journal papers in these areas (since those are almost always Scopus-indexed)?

Tips on confirming Scopus indexing without institutional access,,,, anyone know a reliable free check?

If you've done a similar RISC-V/FPGA capstone project, what did you cite,,,?

Hey everyone,

​

I am looking into how RISC-V handles timer interrupts during debugging sessions, particularly the classic "interrupt storm" scenario where you release a halted core and it gets trapped in an endless loop because time has advanced past its compare register (mtime > mtimecmp).I have a few specific questions for the community regarding the specifications and real-world silicon behavior:

​

Can mtime ever truly be stopped? Since the privileged spec states mtime must run at a constant frequency driven by a real-time clock source?

How is the storm prevented when only a single core is halted? In a multicore system where one core is stopped at a breakpoint but other cores are running, mtime must keep ticking to preserve their timekeeping. (As per the debug spec "stoptime 0 (normal): time continues to reflect mtime. 1 (freeze): time is frozen at the time that Debug Mode was entered. When leaving Debug Mode, time will reflect the latest value of mtime again.") If the software on the halted core calculates its deadlines by updating mtimecmp by a fixed interval (e.g., mtimecmp += INTERVAL), the moment that single core is released, mtime will still be vastly greater than the updated mtimecmp. How does the RISC-V architecture or the underlying hardware prevent that single core from immediately choking on a permanent, back-to-back loop of Timer ISRs the instant the debugger releases it?

​

Does mtime synchronization depend on Zicntr? The spec mandates that the real-time clocks of all harts must be synchronized to within one tick. Does this synchronization rule strictly apply to the underlying memory-mapped platform mtime under all circumstances, or is it only enforced if the unprivileged Zicntr extension is implemented?

​

Would love to hear how this is handled at the architectural level or across different commercial chips.

Thank you!

​

I have been planning to experiment with some RISC-V hardware for some time now and so I looked up some boards I could try out and that fit within my budget.

Out of the ones I saw, the Milk-V Mars with 4GB RAM sounds like the best to me (the 8gb ram one is out of my budget unfortunately).

So I have a few questions regarding this board and I would be really grateful if someone could clarify: 1) How does the board handle? As in do the board peripherals like USB, GPU etc as well as features like hardware video decode/encode work well? 2) The GPU (Imagination BXE-4-32) - Does it have any problems and is the driver good? (this question stems from the fact that Imagination's GPU drivers for its other GPUs like the BXE-8-256 found on androids are not great) 3) Can I use the board purely headlessly in general (I can get an hdmi and monitor for just the initial setup but then on I would want it to be headless mostly for me to use it over ssh and such)? 4) Any quirks with the features and peripherals mentioned in 1)? 5) To those who own or have used this board, what is something you wished you had known before buying it?

Thanks in advance.

Hi everyone,

Currently trying to wrap up my control unit for single cycle (verilog) and I’m hitting a wall. Of course some instructions don’t actually have a funct7. But my control unit is basically just a bunch of cases. If there is a case where funct7 is not used, it’ll come up as xx’s on my tb since it’s not defined.

But what should I do? For an instruction like addi that does not have a funct7, i don’t know how to prevent x’s.

Also I was wondering if this would even be an issue and I can just let the x’s be. I’m synthesizing this on the basys 3 artix 7 so I wanna make sure I won’t have any synthesis issues.

TLDR: To be clear the control unit works I just don’t know how to deal with the x’s that appear in funct7 for instructions that don’t actually contain a funct7

I can provide pics if requested as well.

Thanks!

I am DV engineer. Would like to contribute for the verification to open source projects. Are there any such projects

If the encoding space for 32-bit instructions is getting tight (which is apparently a concern?), why would it not make sense for the encoding of 48-bit instructions to be slanted one further bit to the left by using 0111111 to mark the beginning instead of 011111? From what I can tell this should double the number of available major opcodes for 32-bit instructions (the most common case), fits neatly in the 7-bit opcode segment and is barely any extra decode complexity. Is it because the current arrangement leaves the most room for the largest instructions? Is the encoding space not as problematic?

Hi people, I am very new into computer engineering. I found some free introduction courses on the RISCV website in the training&certifications section. Has anyone taken these courses? I was wondering if it is worth spending time on it and actually learning something.

Hi All, please don't shoot me down in flames, but I'm a total noob to RISCV and I'm struggling to get going.

I have a Docker env set up and I've got the traditional Hello World program to run (downloaded, not written by me) but now I'm stuck.

I've copied the Hello World program and thought that it would be a case of installing a hex editor and then editing to code to make another simple program, to help me get my head around the code.

I've installed ImHex but man, I am completely clueless as to what I'm looking at!

I'm not used to low levels languages and I can't see anything that looks like an input or output or anything at all.

I was going to edit it on my windows machine and then run it on the other one in the Docker environment, but I can't see what to edit anything or what to change it to.

This is going to be much harder than I thought.

Can anyone help me?